Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Akihito Tanabe

Shigeru Tohyama

Nobuhiko Mutoh

Yukiya Kawakami

Yoshiharu Kudoh

Junichi Fujikata

Toru Tatsumi

Jun Ushida

Daisuke Okamoto

Kenichi Nishi

To suppress short channel effects and obtain a high driving current by means of a semiconductor device having an MISFET wherein a material having high mobility and high dielectric constant, such as germanium, is used for a channel. A p-type well is formed on a surface of a p-type silicon substrate. A silicon germanium layer having a dielectric constant higher than that of the p-type silicon substrate is formed to have a thickness of 30 nm or less on the p-type well. Then, on the silicon germanium layer, a germanium layer having a dielectric constant higher than that of the silicon germanium layer is formed to have a thickness of 3-40 nm by epitaxial growing. The germanium layer is permitted to be a channel region; and a gate insulating film, a gate electrode, a side wall insulating film, an n-type impurity diffusion region and a silicide layer are formed.

Semiconductor device

A semiconductor device includes a bonding pad, and an area designation marking, wherein the bonding pad includes a first region, a second region, and a third region placed between the first region and the second region, wherein the area designation marking includes a first area designation mark configured to designate a first boundary between the first region and the third region and a second area designation mark configured to designate a second boundary between the second region and the third region, wherein the first region and the second region are configured to be contacted with a test probe. The first area designation mark includes a first notch or a first protrusion. The second area designation mark includes a second notch or a second protrusion. The first area designation mark includes a first pair of notches that is linearly spaced apart from each other to designate the first boundary line.

Semiconductor device and manufacturing method thereof

The lattice mismatching between a Ge layer and a Si layer is as large as about 4%. Thus, when the Ge layer is grown on the Si layer, penetration dislocation is introduced to cause leakage current at the p-i-n junction. Thereby, the photo-detection sensitivity is reduced, and the reliability of the element is also lowered. Further, in the connection with a Si waveguide, there are also problems of the reflection loss due to the difference in refractive index between Si and Ge, and of the absorption loss caused by a metal electrode. In order to solve said problems, according to the present invention, there is provided a vertical type pin-SiGe photodiode having a structure which is embedded in a groove formed in a part of a Si layer, in which a p-type or n-type doped layer is formed in a lower section of the groove, and in which a i-SiGe layer having a rectangular shape or a reverse tapered shape is formed on a layered structure formed by laminating a i-Si layer and a SiGe buffer layer on the lower section and the side wall of the groove. Further, in an optical connection section with a Si waveguide, impedance matching is effected by the layered structure composed of the i-Si layer and the SiGe buffer layer, and an upper metal layer is separated therefrom so that a poly-Si bridge structure is employed to electrically connect the upper metal layer therewith.

SiGe photodiode

The semiconductor device having a bonding pad is provided. The bonding pad enables highly reliable connection and high flexibility of the selection of the area to be bonded. The semiconductor device includes a bonding pad and an area designation marking. The bonding pad includes a first region, a second region and a third region formed between the first region and the third region. The area designation marking includes a first notch for designating a first boundary of the first region and the third region and a second notch for designation a second boundary of the second region and the third region. Any of the first region and the second region can be used as the region where the scratch formed by a probing process is to be formed.

Semiconductor device with multiple designation marks

An objective of this invention is to allow each process of contacting of a test probe and bonding to be reliably conducted within a given region. A semiconductor devicehas a probing markforming region; a bonding padhaving a bonding regionand a check markseparate from the bonding padIn the configuration, the probing markforming region and the bonding regioncan be identified on the basis of a planar shape of the check mark

Semiconductor device and manufacturing process therefor

A charge storing layer of a photodiode having an N-type conductivity includes an N -type additional implant area in the vicinity of a junction between the charge storing layer and an isolation region. The additional implant area provides an increase of stored charge and suppression of increase of the pulse voltage for a substrate shutter, and can be made to have a smaller width within a current design rule.

Solid state imaging device and method for manufacturing the same

This invention provides a manufacturing process for a charge transfer device comprising an N-type well formed in a P-type well on a semiconductor substrate for transferring a signal charge, an N&plus; region formed on both sides along the charge transfer direction of the N-type well and containing a dopant in a higher concentration than that in the N-type well, a P-type region formed around the N&plus; region, and a gate electrode covering the N&plus; region and the N-type well and formed via a gate insulator, comprising ion-implanting an N-type dopant into the region to be the N-type well and the N&plus; region using the first mask and ion-implanting a P-type dopant into the region to be the N-type well using the second mask. Thus, there can be provided a charge transfer device which has a structure where there is an N&plus; region on both sides of the N-type well, a large maximum transferable charge and a compact CCD with a width up to 3 times the minimum design dimension.

Charge transfer device and a manufacturing process therefor

A solid state image pickup device has a photo diodes for producing charge packets from image-carrying light, a vertical overflow drain formed under the photo diodes, charge transfer channel regions selectively connected to the photo diodes through transfer gate transistors, resistive gate electrodes capacitively coupled to said charge transfer channel regions, respectively, and a pulse signal source connected to far ends of the resistive gate electrodes and near ends of the resistive gate electrodes closer to a horizontal charge transfer unit, and the pulse signal source produces a potential gradient in the charge transfer channel regions after transfer of the charge packets to the charge transfer channel regions so that the charge packets are conveyed through the horizontal charge transfer unit without a large horizontal charge transfer signal.

Solid-state image pickup device having vertical overflow drain and resistive gate charge transfer device and method of controlling thereof

Disclosed is a photoelectric transducer having a photodiode that is formed on a second-conductivity-type well and is composed of a first-conductivity-type region to accumulate signal charge when light is supplied and a first second-conductivity-type region formed on the first-conductivity-type region. The first second-conductivity-type region is separated from a second-conductivity-type device separation region and is connected to the second-conductivity-type device separation region at part of the circumference of the first second-conductivity-type region through a second second-conductivity-type region that is formed to be at least partially shallower than the first second-conductivity-type region. Also, disclosed is a solid-state image sensing device equipped with the photoelectric transducer.

Photoelectric transducer and solid-state image sensing device using the same

This invention provides a manufacturing process for a charge transfer device comprising an N-type well formed in a P-type well on a semiconductor substrate for transferring a signal charge, an N&plus;region formed on both sides along the charge transfer direction of the N-type well and containing a dopant in a higher concentration than that in the N-type well, a P-type region formed around the N&plus; region, and a gate electrode covering the N&plus; region and the N-type well and formed via a gate insulator, comprising ion-implanting an N-type dopant into the region to be the N-type well and the N&plus; region using the first mask and ion-implanting a P-type dopant into the region to be the N-type well using the second mask. Thus, there can be provided a charge transfer device which has a structure where there is an N&plus; region on both sides of the N-type well, a large maximum transferable charge and a compact CCD with a width up to 3 times the minimum design dimension.

There is provided a charge transfer device including (a) a charge transfer channel for transferring signal charges therethrough, (b) a floating diffusion region for accumulating therein charges transferred from the charge transfer channel, (c) a field effect transistor for resetting the floating diffusion region so that the floating diffusion region is at a predetermined potential and (d) a bias charge input section through which a bias charge is supplied and which is connected to either the charge transfer channel or the floating diffusion region. The field effect transistor includes a reset gate electrode and a reset drain. The charge transfer channel located below the reset gate electrode is designed to receive either a potential lower than a potential of the reset drain when the floating diffusion region is reset in the case that charges to be transferred are electrons, or a potential higher than a potential of the reset drain when the floating diffusion region is reset in the case that charges to be transferred are holes. The above-mentioned charge transfer device ensures to reset the floating diffusion region regardless of whether a potential in the reset drain is greater or smaller than a potential in a channel located below the reset gate electrode.

Charge transfer device and method of driving the same

A two-dimensional image sensor comprises a matrix array of photodiodes and multiple vertical shift registers horizontally divided into an imaging part and a memory part. During a vertical blanking period, the imaging part receives charge packets from the photodiodes and shifts the charge packets via the memory part to a matrix array of storage cells. During a subsequent horizontal blanking period, the charge packets are restored from the storage cells to the memory part and shifted downwards by the distance of a row so that the charge packets of bottom row are shifted our into a horizontal register. Remaining charge packets are then withdrawn from the memory part to the storage cells and stored therein during a subsequent horizontal scan period. During this horizontal scan period, the memory part is maintained at such a voltage that no dark currents substantially exist and the charge packets in the horizontal register are sequentially delivered to external circuitry.

Two-dimensional CCD having storage cells for withdrawing charge packets

Disclosed is a photoelectric conversion device in which a photodiode capacitance is increased. A transparent electrode is formed between a reflecting plate and a photodiode constituting a unitary picture element of a CCD image sensor. It is so formed that light is incident from the rear surface and the loop of the standing wave of the light comes on a platinum silicide film, thereby achieving the effective absorption of the incident light. The transparent electrode is formed between the reflecting plate and the photodiode in opposition to the platinum silicide film. The capacitance between the transparent electrode and the platinum silicide film can be utilized as photodiode capacitance. Optically optimum thickness is assured by individually forming the reflecting plate which optimizes optical properties represented by the absorption of the incident light, and the transparent electrode used for increasing the photodiode capacitance, and also applying a pulse voltage to the transparent electrode at a given timing in such a manner that the potential at the time of resetting of the photodiode potential is lower than that obtained when the charge is accumulated.

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Tokyo, Japan

Akihito Tanabe