Lsi Logic Corporation

Akihisa Ueno

Ronald J Nagahara

Jayanthi Pallinti

James J Xie

Hiroshi Mizuno

Kostas Amberiadis

Osamu Kinoshita

Tetsuaki Murohashi

Yoshifumi Sakuma

The invention provides a process for selectively polishing a main electrically conductive layer of an integrated circuit structure by the steps of forming a polishing barrier layer over depressed regions of the main electrically conductive layer; and polishing the portion of the main electrically conductive layer not covered by the polishing barrier layer. The integrated circuit structure treated by the process of the invention contains one or more openings in a layer of dielectric material, and the main electrically conductive layer fills the one or more openings such that the depressed regions of the main electrically conductive layer overlie said one or more openings.

Process for selective polishing of metal-filled trenches of integrated circuit structures

Process for planarization of metal-filled trenches of integrated circuit structures by forming a layer of planarizable material over the metal layer prior to planarizing

A method for chemical-mechanical polishing of a layer that is deposited on a surface of an integrated circuit substrate is described. The method includes: (1) immobilizing the integrated circuit substrate using a substrate holder such that the integrated circuit substrate surface is positioned against a surface of a polishing pad, which is mounted on a supporting surface; (2) a first stage of polishing the substrate surface including maintaining a predetermined difference between the rotational velocity of the polishing pad and the rotational velocity of the substrate holder allowing an endpoint of the chemical-mechanical polishing process of the layer to be detected; and (3) a second stage of polishing the substrate such that the rotational velocity of the polishing pad and the rotational velocity of the substrate holder are substantially the same to produce a substantially planar substrate surface.

Method and apparatus for chemical-mechanical polishing

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Cupertino, CA, United States of America

Akihisa Ueno