Hitachi, Ltd.

Akihisa Ueda

Motoo Uno

Masuo Furutono

Kenji Taguchi

Toshio Ogata

Mitsuyoshi Satoo

Hiroshi Kitahata

A programmable controller which handles both bit data and word data includes a memory having a memory area which is divided into blocks each having a predetermined length which corresponds to the number of bits constituting one word. An address is provided to each of the blocks, and one bit data or one word data is selectively stored in each of the blocks. Thus, the memory area is provided with flexibility, and the preparation of a program is facilitated.

Bit and word memory allocation for a programmable controller

A paper sheet handling apparatus including a plurality of sheet accumulating portions and a sheet conveyor. A pointed separator is mounted on the conveyor for movement into a stack of paper sheets accumulated in one sheet accumulating portion to divide the stack into two parts with a gap formed therebetween. Gripping fingers mounted on the conveyor are moved into gripping engagement with one of the divided parts of the stack and then retracted to transfer the gripped part of the stack onto the conveyor. Holding members on the conveyor are movable into the gap to hold the paper sheets of the other part of the stack. The conveyor is movable to convey the gripped paper sheets to another sheet accumulating portion. The gripping fingers are again moved to transfer the thus conveyed sheets to the other sheet accumulating portion. Sensors are mounted on the conveyor to determine whether or not the paper sheets to be transferred are directly positioned relative to the sheet transferring members of the sheet accumulating portions and, if not correctly positioned, corrective action is effected in response to the determined incorrect positioning.

Paper sheet depositing and dispensing apparatus, abnormality recovery

A system arrangement for detecting the uncontrollable operation of a control system includes an interrupt signal generating circuit which issues the interrupt signal to the central processing unit (CPU) on a hardware basis so that the CPU is interrupted at a constant interval even during the uncontrollable operation of the control system. The CPU responds to the interrupt signal to initiate the interrupt processing routine, which then detects the state of uncontrollable operation basing on the trace of the computational processes carried out by the CPU.

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Shibatashi, Japan

Akihisa Ueda