Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Other

Renesas Technology Corp.

Hatachi Ltd

Hitachi, Ind.

Akihisa Uchida

Katsumi Ogiue

Yoichi Tamaki

Toshihiko Takakura

Masao Kawamura

Keiichi Higeta

Daisuke Okada

Takeo Shiba

Kazuhiko Sagara

Shigeo Kuroda

Mikinori Kawaji

Ichiro Mitamura

Takahiro Onai

Kiyoji Ikeda

Nobuhiko Ohno

Toru Koizumi

Shinji Nakashima

Toshio Sasaki

Tokuo Kure

Noriyuki Sakuma

Toshio Yamada

Katsuyoshi Washio

Yuji Yatsuda

Tohru Nakamura

Masanori Odaka

Tetsuya Hayashida

Akinobu Watanabe

Hiromichi Enami

Satoru Isomura

Kunihiko Yamaguchi

Kiichiro Mukai

Nobuo Tamba

Kazuo Nakazato

Masato Iwabuchi

Masami Usami

Yasuhiro Fujimura

Yasushiro Nishioka

Hiroshi Shinriki

Shinji Nakajima

Sohei Omori

Toru Nakamura

Kunihiko Watanabe

Daisuke Okaka

Etsuko Iwamoto

Yoshino Sakai

Hiroyuki Ikeda

Kaoru Ohgaya

Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.

Method of manufacturing a semiconductor device

A semiconductor memory device for use in a digital data processor together with a central processing unit (CPU) receives address signals which are validated for a time period n times as long as the machine cycle of the CPU, and it stores therein input data items which are validated for a cycle equal to the machine cycle of the CPU or delivers therefrom output data items which are validated for a cycle equal to the machine cycle of the CPU.

Semiconductor integrated circuit device and digital processor employing

An integrated circuit including latch circuits disposed on the input and output sides of an object circuit the delay time of which is to be measured, respectively, and a variable delay circuit capable of arbitrarily delaying a timing signal supplied from outside or a timing signal generated inside the integrated circuit by an instruction from outside. The timing signal and a delay signal obtained by delaying the input signal by the variable delay circuit are supplied as clock signals to the latch circuits, and the signal passing through the variable delay circuit is fed back to the input side so as to constitute an oscillation circuit, the oscillation signal of which can be outputted to outside. A signal delayed by a desired time can be automatically generated inside the semiconductor integrated circuit on the basis of this timing signal.

Semiconductor integrated circuit device having circuit inspection

A semiconductor integrated circuit device having a structure in which each of the following regions, that is, a first region for forming the base and emitter regions of each of the bipolar transistors, a second region for forming the collector lead-out region of the bipolar transistor, and a third region for forming each of the MISFETs, is projected from the main surface of a semiconductor substrate, whereby it is possible to effect isolation between the MISFETs and between these MISFETs and the bipolar transistors with the same isolation structure and in the same manufacturing step as those for the isolation between the bipolar transistors. In this device, furthermore, the base region of the bipolar transistor is electrically and self-alignedly connected to a base electrode which is formed over the main surface so as to surround the emitter region. The bipolar transistor is characterized as a self-alignment transistor and that the insulating side wall spacers corresponding to the gate and base (emitter) electrodes are formed by a same lever.

Semiconductor integrated circuit device forming on a common substrate

A semiconductor device employing a new isolation process is disclosed, wherein an isolation area is a region in which a burying material is buried in a deep groove formed in a semiconductor body with a substantially constant width by anisotropic dry etching, semiconductor elements are formed in selected ones of semiconductor regions isolated by the isolation area, and others of the semiconductor regions, with no semiconductor element formed therein, have their whole surface covered with a thick oxide film which is produced by the local oxidation of the semiconductor body. The new isolation process is well-suited for a bipolar type semiconductor device, wherein the deep groove is formed so as to reach a semiconductor substrate through an N.sup.+ -type buried layer, and a thick oxide film formed simultaneously with the aforementioned thick oxide film isolates the base region and collector contact region of a bipolar transistor.

Method of manufacturing semiconductor device with constant width deep

A bipolar SRAM which includes a forward bipolar transistor and a reverse bipolar transistor on an identical semiconductor substrate, is disclosed. Concretely, the base region of the reverse bipolar transistor is formed at a deeper position of the substrate than the base region of the forward bipolar transistor, thereby to heighten the cutoff frequency f.sub.T of the reverse bipolar transistor.

Semiconductor integrated circuit device having bipolar memory, and

A bipolar type of semiconductor integrated circuit device is provided with U-shaped grooves which are formed by cutting a main surface of a semiconductor body to form isolation regions between bipolar transistors. A silicon oxide film can be formed in the U-shaped grooves by thermal oxidation simultaneously with the formation of a silicon oxide film used to form isolation regions between each collector contact region and base region. No separate step is needed for forming the silicon oxide film between the collector contact region and the base region. The thickness of the silicon oxide film can be controlled, and has a sufficient thickness even at its two edges, i.e., at its boundaries with the U-shaped grooves, so that the bipolar transistors exhibit good electrical characteristics. Namely, the collector resistance thereof does not increase, and the breakdown voltage at the pn junction between the collector region and the base region does not decrease. The U-shaped grooves can each comprise narrow and deep sub-grooves, with thick oxide films formed on the surfaces of the sub-grooves and a thick oxide film formed on a surface of an area between the sub-grooves, and with wiring formed on the oxide on the area between the sub-grooves.

Process of manufacturing semiconductor integrated circuit device having

This invention relates to a semiconductor integrated circuit device including highly self-aligned bipolar transistors. The semiconductor integrated circuit device a semiconductor body at least a first protruding portion and a hollow portion, disposed as a trench. The hollow portion being adjacent to the first protruding portion and being lower than an upper surface of the first protruding portion and including an isolation groove which is formed along a side surface of the protruding portion and in self-alignment with a peripheral edge portion of the upper surface of the first protruding portion. The device also has insulating material formed on a surface of the hollow portion so as to fill the insulation groove, a first semiconductor region of a first conductivity type formed in the first protruding portion, a portion of said first semiconductor region being exposed to the side surface of the protruding portion, a second semiconductor region of a second conductivity type opposite to the first conductivity type formed in the first protruding portion on the first semiconductor region, a third semiconductor region of the second conductivity type formed in the first protruding portion under the first semiconductor region and a polycrystalline silicon film formed on the insulating material in contact with at least the portion of the first semiconductor region exposed to the side surface of the protruding portion.

Semiconductor integrated circuit device with isolation grooves and

Method of fabricating a semiconductor substrate, and semiconductor

There is implemented memory cells and corresponding signal lines associated therewith in bipolar type static random access memories employing wirings of multi-layer construction for transmitting a common signal therethrough such as with respect to the individual word lines. The word lines implemented are formed from at least a pair of stacked conductive layers and which layers have interposed therebetween an insulating film. The pair of layers form a pair of wiring lines wherein together they form a work line and wherein the wiring lines are, furthermore, interconnected at predetermined intervals along the lengths thereof. This leads to the ability to decrease the chip size of semiconductor integrated circuits noting that a decrease in the voltage drop of a signal line results, and to prevent electromigration in the signal (wiring) lines. There is, furthermore, implemented a current line formed from a conductor layer which is extended along the direction of the word lines over a region, together with the word lines, where the memory cells are formed.

Bipolar SRAM having word lines as vertically stacked pairs of conductive

Process of manufacturing semiconductor integrated circuit device and

A multilayer semiconductor integrated circuit having a plurality of wiring layers in which at least the lines of a lower layer are extended on wiring channel regions arranged in a grid. Dummy pedestals are formed of the same conductive layer as that forming the lines of the lower layer and are arranged in the intersecting areas of the wiring channel regions where none of the lines of the lower layer is placed. A method of manufacturing such a semiconductor integrated circuit comprises steps of preparing dummy pedestal layout data for arranging the dummy pedestals in all the intersecting areas of the wiring channel regions and line layout data for forming the lines of the lower layer on predetermined wiring channels among all the wiring channel regions, and combining the dummy pedestal layout data and the line layout data by logical sum (OR).

Semiconductor integrated circuit with dummy pedestals

There is implemented memory cells and corresponding signal lines associated therewith in bipolar type static random access memories employing wirings of multi-layer construction for transmitting a common signal therethrough such as with respect to the individual word lines. The word lines implemented are formed from at least a pair of stacked conductive layers of a material whose principal component is aluminum and which layers have interposed therebetween an insulating film. The pair of layers form a pair of wiring lines corresponding together to a word line and wherein the wiring lines are, furthermore, interconnected at predetermined intervals along the lengths thereof. This leads to the ability to decrease the chip size of semiconductor integrated circuits noting that a decrease in the voltage drop of a signal line results, and to prevent electromigration in the signal (wiring) lines.

Bipolar static RAM having two wiring lines for each word line

A semiconductor device is disclosed, which includes bipolar transistor each having an emitter, base and collector formed inside each protruding portion of a semiconductor substrate, and trenches for device isolation. The bipolar transistor and the trench are spaced apart from each other by a predetermined spacing. According to this arrangement, the width of a base contact becomes uniform and any change of transistor characteristics can be prevented effectively.

Semiconductor device

A semiconductor integrated circuit device is provided with polycrystalline silicon filling U-grooves etched in a semiconductor substrate to form isolation regions which prevent any short-circuiting between the polycrystalline silicon and electrodes or wiring formed on the semiconductor substrate. A silicon dioxide film is formed within the U-grooves, and a silicon nitride film and a silicon dioxide film are further formed thereon. The silicon nitride film has a high hardness which suppresses the development of crystal defects in the peripheral active regions due to the expansion of the surface of the polycrystalline silicon when it is oxidized. When the surface of the polycrystalline silicon is oxidized, the oxidation proceeds along the oxide film over the nitride film, so that the whole of the oxide film is formed thickly. Therefore, the silicon nitride film and the silicon dioxide film are provided with an increased margin against the etching used for forming contact holes.

Semiconductor body, and device formed therefrom, having grooves with

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Tachikawa, Japan

Akihisa Uchida