Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Renesas Technology Corp.

Akihisa Iwasaki

Kazuo Tomita

Akira Ueki

Susumu Matsumoto

Yasutaka Nishioka

Keiji Hashimoto

Dai Motojima

Chikako Chida

Michiya Takahashi

Mitsuru Sekiguchi

A semiconductor device includes a stacked via structure including a plurality of first vias formed over a substrate, a first interconnect formed on the plurality of first vias, a plurality of second vias formed on the first interconnect, and a second interconnect formed on the plurality of second vias. One of the first vias closest to one end part of the first interconnect and one of the second vias closest to the one end part of the first interconnect at least partially overlap with each other as viewed in the plane, and the first interconnect has a first extension part extending from a position of an end of the first via toward the one end part of the first interconnect and having a length which is more than six times as long as a via width of the first via.

Multilayer interconnects with an extension part

A semiconductor device includes: a first insulation film formed over a semiconductor substrate; and a plurality of first interconnects selectively formed in the first insulation film. A plurality of gaps are formed in part of the first insulation film located between adjacent ones of the first interconnects so that each of the gaps has a cylindrical shape extending vertically to a principal surface of the semiconductor substrate. A cap film is formed of metal or a material containing metal in upper part of each of the first interconnects.

Semiconductor device and method for fabricating the same

First wirings and first dummy wirings are formed in a p-SiOC film formed on a substrate. A p-SiOC film is formed, and a cap film is formed on the p-SiOC film. A dual damascene wiring, including vias connected to the first wirings and the second wirings, is formed in the cap film and the p-SiOC film. Dummy vias are formed on the periphery of isolated vias.

Method of manufacturing interconnecting structure with vias

Growing community of inventors

Shiga, Japan

Akihisa Iwasaki