Sharp Kabushiki Kaisha Corporation

Akihisa Iwamoto

Hideki Morii

Takayuki Mizunaga

Satoshi Horiuchi

Kohji Saitoh

Masami Ozaki

Masaki Uehata

Tomohiko Nishimura

Jun Nakata

Shinya Tanaka

Kazushige Miyamoto

Masakazu Takeuchi

Kei Ikuta

Masahiro Hirokane

Yuuki Ohta

Kazuya Nakaminami

Tetsuo Kikuchi

Yasuaki Iwase

Akira Tagawa

Takaharu Yamada

Hiroshi Nakanishi

Osamu Miyazaki

Chikao Yamasaki

Kazuki Ohfuku

Toshiyuki Makii

Yasukazu Tomita

Akihiro Hada

Masuji Tanimura

Masami Inoue

Hideji Morii

A display device includes a display panel in which display pixels including colored pixels of a plurality of colors are arranged, an illumination device including a light source and configured to illuminate the display panel with light, and a control substrate configured to control drive of the display pixels, wherein the control substrate includes a display data generation circuit configured to generate display data for driving the display pixels, based on image data supplied from an external image signal supply source, a detection circuit configured to detect a change in luminance light modulation data for modulating luminance of the light source, supplied from an external image signal supply source, and a display data correction circuit configured to correct the display data, based on an output value of the detection circuit.

Display device comprising a control substrate configured to control drive of display pixels

The invention provides a gate-in-panel display device capable of preventing deterioration of thin-film transistors during pause drive, as well as a method for driving the same. At the end of a drive period, an active clear signal is provided to thin-film transistors in unit circuits, each thin-film transistor being connected to either a first or second node at a gate terminal, thereby bringing the thin-film transistors into ON state. As a result, the voltages of the first and second nodes are set to a reference voltage. Thus, even if a pause period lasts for a long period of time, the gate terminals of the thin-film transistors are not subjected to sustained voltage application, leading to no threshold voltage shifts.

Display device and method for driving same

A gate driver () which is provided by an IGZO-GDM and a level shifter circuit () are connected to each other via a first through a fifth wires (OLthrough OL). Each wire (OL) is connected to a discharge unit (). If an electric power supply to a first through a fifth output circuits (OCthrough OC) in the level shifter circuit () becomes lower than a lower operation limit value during a power-off sequence which is supposed to remove a residual charge from inside a panel, outputs from the first through the fifth output circuits (OCthrough OC) assume a high-impedance state, whereupon a potential on each wire (OL) is drawn by a discharge unit () into a ground potential. Therefore, residual charge inside the panel is removed quickly and stably when power supply is shut off.

Display device and method of driving the same

In a display device that can use a low frequency drive method, in the case of low frequency drive, in a data correction unit () of a display control circuit (), a pixel grayscale value is set such that the differential value between the potential difference between the pixel electrode and the common electrode when a voltage of positive polarity is applied and the potential difference between the pixel electrode and the common electrode when a voltage of negative polarity is applied becomes larger than during normal drive. With this, a correction amount (shift amount) is made larger during low frequency drive than during normal drive, whereby flickers and ghosting during low frequency drive are prevented.

Display device that compensates for changes in driving frequency and drive method thereof

A shift register is configured so that each of first and second intermediate stages includes (i) a first input terminal supplied with a clock signal, (ii) a second input terminal supplied with a clock signal different in phase from the clock signal supplied to the first input terminal, (iii) an output terminal connected to the first input terminal via an output transistor, and (iv) a setting circuit, which is connected to the second input terminal and the output transistor, for setting an electric potential of a control terminal of the output transistor, the second intermediate stage includes a control circuit which is (i) connected to the setting circuit of the second intermediate stage and (ii) supplied with a control signal, an operation period (i) starts at a time when a shift start signal supplied to an initial stage is activated and (ii) ends at a time when an output of a final stage changes from activation to inactivation, and when the clock signal supplied to the first input terminal of the second intermediate stage is initially activated after the operation period starts, the clock signal supplied to the second input terminal of the second intermediate stage is inactive.

Shift register, driver circuit and display device

A liquid crystal display device includes: a data signal line; a scan signal line; a pixel electrode; a transistor connected to (i) the data signal line, (ii) the scan signal line, and (iii) the pixel electrode; and a common electrode, the liquid crystal display device being configured to turn on the transistor during a power-off sequence by causing a change in an electric potential of the scan signal line, the electric potential of the scan signal line reaching a first electric potential at a first timing after the change is initiated, and the common electrode being in an electrically floating state at a second timing which comes after the first timing. This, in a case where the transistor is turned on in preparation for an operation to turn off a power source of the liquid crystal display device, makes it unlikely for a DC voltage to be applied across a pixel even if potential variation (kickback) occurs at the pixel electrode in reaction to a change in status of the transistor from an on state to an off state.

Liquid crystal display device and liquid crystal display device driving method

Provided are: a liquid crystal display device capable of rapidly removing residual electric charges in a panel when a power supply is turned off, and in particular, suitable for a case where IGZO-GDM is adopted; and a driving method of the liquid crystal display device. In the liquid crystal display device, when an OFF state of the power supply is detected, a power supply OFF sequence including an initialization step, a first discharge step and a second discharge step is executed. In the initialization step, only a clear signal (H_CLR) among GDM signals is set at a high level, and a state of each of bistable circuits which constitute a shift register is initialized. In the first discharge step, only the clear signal (H_CLR) among the GDM signals is set at a low level, all of gate bus lines are turned to a selected state, and electric charges in pixel formation portions are discharged. In the second discharge step, the clear signal (H_CLR) is set at the high level, and electric charges on floating nodes in each of the bistable circuits are discharged.

Liquid crystal display device and drive method for same

The invention provides a liquid crystal display device that includes an IGZO-GDM which can quickly remove a residual charge in a panel when the power supply is turned off, and a driving method of the liquid crystal display device. Each bistable circuit that configures a shift register includes a thin film transistor TI for increasing a potential of an output terminal based on a first clock, a region netA connected to a gate terminal of the thin film transistor TI, a thin film transistor TC for lowering a potential of the region netA, and a region netB connected to a gate terminal of the thin film transistor TC. In such a configuration, a power supply off sequence includes a display off sequence and a gate off sequence. The gate off sequence includes at least a gate-bus-line discharge step (tto t), a netB discharge step (tto t), and a netA discharge step (tto t).

Liquid crystal display device and driving method thereof

A display panel drive circuit includes a shift register constructed of unit circuits connected in stages. The unit circuits generate signal line selection signals, respectively, which signal line selection signals are made active for a respective certain period of time to form a respective pulse, and the pulses are outputted successively from respective unit circuits in order of ordinal number starting from a first stage until an end stage. In at least one embodiment, each of the unit circuits receive (i) clock signals generated based on a sync signal received from outside of the display panel drive circuit, (ii) a start pulse signal generated based on the sync signal, or a signal line selection signal generated in a stage different from its own stage, and (iii) a clear signal. The clear signal is made active in a case where anomalousness is included in the sync signal, and no pulse is outputted from the shift register until a subsequent vertical scanning period starts. This configuration achieves a display panel drive circuit which prevents display disorder or holds down increase in load given to a power source, each of which occurs in a case where anomalousness is included in the sync signal.

Shift register and liquid crystal display device for detecting anomalous sync signal

Provided is a display device capable of correctly displaying an image when surplus outputs are produced within a driver, regardless of a shifting direction of a shift register within the driver, without bringing about increase in cost and increase in consumption current. A timing controller () is provided with a register () that can store data indicating the length of a horizontal back porch when a shifting direction of a shift register within a source driver () is in a forward direction and data indicating the length of the horizontal back porch when the shifting direction is in an inverse direction. A source-start-pulse generation unit () within the timing controller () refers to the data within the register () according to the shifting direction of the shift register, and generates one of a first source start pulse signal (SSP) for the forward direction and a second source start pulse signal (SSP) for the inverse direction.

Display device with bidirectional shift register and method of driving same

A display device, in at least one embodiment, includes: a gate driver including a plurality of shift register stages each provided so as to correspond to each row, the gate driver outputting a gate signal for turning on switching elements in the each row; and a source driver outputting a data signal in accordance with an image to be displayed. For a row (first row) located at an outermost position from which scanning by use of the gate signal starts, a dummy line is provided. The dummy line is driven by a gate start pulse inputted into a shift register in the first row.

Display device for reducing parasitic capacitance with a dummy scan line

An object is shortening a clock fall-rise period while suppressing an increase in a circuit area, an increase in current consumption, and a cost increase, without generating an abnormal operation, in a shift register within a monolithic gate driver. In a shift register () that operates based on four-phase clock signals, including two-phase clock signals (GCK, GCK) that are provided to odd-order stages and two-phase clock signals (GCK, GCK) that are provided to even-order stages, of which phases are shifted by 90 degrees from each other, a potential of a first clock (CKA) appears as a potential of a scanning signal (GOUT), when a potential of a first node is at a high level, in each stage. In this configuration, the potential of the first node included in each stage is set to a high level based on a pulse of a scanning signal outputted from a pre-stage, and is set to a low level based on a pulse of a scanning signal outputted from a third stage after a stage concerned.

Shift register, scanning signal line drive circuit provided with same, and display device

Each stage that constitutes a shift register includes an output-control thin-film transistor for increasing a potential of a scanning signal based on a first clock (CKA), two thin-film transistors for increasing a potential of a first node connected to a gate terminal of the output-control thin-film transistor, based on a scanning signal outputted from a pre-stage/a latter stage, and two thin-film transistors for decreasing a potential of the first node, based on a scanning signal outputted from a third stage after/a third stage before a stage concerned. The shift register operates based on four-phase clock signals, including two-phase clock signals that are provided to odd-order stages and two-phase clock signals that are provided to even-order stages, of which phases are shifted by 90 degrees from each other.

A liquid crystal display device includes: scanning wires, provided so as to correspond to a plurality of pixels disposed in a matrix manner, to which scanning signals are applied; and signal wires to which data signals are applied, wherein the scanning wires and the signal wires cross each other. TFTs, electrically connected to the scanning wires and the signal wires, each of which is provided in the vicinity of an intersection of the scanning wire and the signal wire, and the TFTs are connected to pixel electrodes. A dummy pixel driven by a dummy signal wire is provided externally adjacent to an endmost pixel column. This brings about a matrix type liquid crystal display device that equalizes capacitive conditions of all the signal wires to each other and can prevent deterioration of display quality that is brought about by a specific portion differently displayed.

Liquid crystal display device

In one embodiment of the present invention, a video signal processing method is disclosed wherein video correction data is read from a ROM and written into an LUT, and the video correction data written in the LUT is used to perform data correction of an externally inputted video signal. The video correction data written in the LUT is updated during the horizontal blanking interval of the video signal.

Growing community of inventors

Osaka, Japan

Akihisa Iwamoto