Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Akihisa Fujimoto

Hiroyuki Sakamoto

Masao Suga

Kosei Okamoto

Atsushi Kondo

Toshitada Saito

Noriya Sakamoto

Shinichi Matsukawa

Katsuyuki Nomura

Taku Nishiyama

Katsuyoshi Watanabe

Masaomi Teranishi

Kenichi Douniwa

Shinji Honjo

Ryo Yonezawa

According to one embodiment of the present disclosure, a semiconductor system may be disclosed. The semiconductor system according to the one embodiment may include, for example, a plurality of electronic devices and a host apparatus. The host apparatus may simultaneously initialize the plurality of electronic devices in units of group.

System, device, and method for initializing a plurality of electronic devices using a single packet

According to one embodiment, a semiconductor device includes a device. The device includes a decoder, a generation circuit, a register, and a modifier. The decoder analyzes a command of a received packet. The generation circuit generates a unique device number in accordance with information in the packet. The register holds the generated unique device number. The modifier updates and outputs the packet. When a packet issued by a host is a command packet, among broadcast packets which return to the host through one or more devices, for determining the unique device number, the command packet includes parameters of an initial value and final value of device number.

Semiconductor device

According to one embodiment, there is provided a memory card including a first surface, a second surface, and 1to Nterminal groups. The first surface includes first to Nrows, where N is an integer of two or greater. The second surface faces the opposite side from the first surface. The 1to Nterminal groups are placed in the first to Nrows. The 1terminal group includes terminals to which differential clock signals are assigned, terminals to which single-ended signals are assigned, and a terminal to which a first power supply voltage is assigned. Kterminal group, where K is an integer no smaller than two and no greater than N, includes terminals to which differential data signals are assigned.

Memory card with multiple modes, and host device corresponding to the memory card

According to one embodiment, a memory card includes a nonvolatile memory and a controller. The controller performs initialization of an interface, determines a maximum performance that can be supported from among a plurality of performance predetermined for stream recording, based on a bus configuration of the interface determined at the interface initialization and a maximum allowable power consumption set during the interface initialization, and generates a data set stored in a power state register specified by an NVMe™ standard, which is a power state set in which each of all performance smaller than the determined maximum performance among the plurality of performance corresponds to a power state, to indicate a list of the performance which can be supported for a host.

Memory card and host device

According to one embodiment, a semiconductor memory device includes a housing and terminals. The housing has a first end edge extending in a first direction and a second end edge opposite to the first end edge. The terminals include signal terminals and include first terminals, second terminals, and third terminals. The first terminals are arranged in the first direction at a position close to the first end edge. The second terminals are arranged in the first direction with intervals at a position closer to the first end edge than the second end edge. The first plurality of terminals are closer to the first end edge than the second plurality of terminals are. The third terminals are arranged in the first direction with intervals at a position closer to the second end edge than the first end edge.

Semiconductor memory device

According to one embodiment, when a current consumption class supported by a removable memory device is another current consumption class different from a first current consumption class with a largest current consumption value among plural types of current consumption classes, the first current consumption value consumed from a first power by the removable memory device is smaller than or equal to a third permissible current value for a first power defined in the other current consumption class; and a second current consumption value consumed from a second power by the removable memory device is smaller than or equal to a fourth permissible current value for the second power defined in the other current consumption class.

Removable memory device

A host apparatus, into which a card having a nonvolatile semiconductor memory is inserted, issues a check command to the card. The check command instructs to send information on whether the card supports a termination process in which the card shifts into a state ready for a stop of power supply from the host apparatus.

Card and host apparatus

According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

Interface system

According to one embodiment, an information processing apparatus includes a connecting portion connectable to a removable memory device and a power supply circuit configured to apply a first voltage and a second voltage to the removable memory device. When the removable memory device is connected to the connecting portion, one of a pair of first feedback wires is electrically connected to one of the first power supply terminals to which the first voltage is applicable, and the other of the pair of first feedback wires is electrically connected to one of the power supply ground terminals connectable to a ground level, the power supply circuit is configured to control the first voltage, based on a voltage between the pair of first feedback wires.

Information processing apparatus

According to one embodiment, a memory device includes a nonvolatile semiconductor memory having physical storage areas that includes a user area externally accessible and are divided into management units and a control unit. The control unit receives a control command having a first argument to designate a sequential write area and a read command or a write command, assigns a management unit represented by an address of the read command or the write command as the sequential write area, and changes memory access control by judging whether an address of a memory access command to access the user area indicates access in the sequential write area whose size is equivalent to the management unit.

Memory device and host device

According to one embodiment, an information processing apparatus includes a connector into which a first-type semiconductor storage device operating with n types of power supply voltages or a second-type semiconductor storage device operating with m types of power supply voltages less than the n types of power supply voltages is capable of being placed. The apparatus checks whether or not a notch is formed at a predetermined position of a semiconductor storage device placed into the connector, and supplies the m types of power supply voltages to the semiconductor storage device when the notch is formed at the predetermined position.

Information processing apparatus, information processing system, and semiconductor storage device

According to one embodiment, a first power-supply voltage is applied to I/O cells, an I/O cell connected to a clock terminal is initially set to a threshold of a second voltage signaling, an I/O cell connected to a command terminal and I/O cells connected to data terminals are initially set as an input, and when a clock control unit detects receipt of one clock pulse and a signal voltage control unit detects a host using the second voltage signaling, a signal voltage control unit drives the I/O cell of a first data terminal high level after a second power-supply voltage is applied to I/O cells and the threshold of a second voltage signaling is set to I/O cells of the clock, command and data terminals.

Host apparatus and extension device

According to one embodiment, while a memory card is in a second operation mode, a host controller monitors a reset signal for the second operation mode and detects that an error occurs in the second operation mode in the condition that a period of time during which both a card presence signal and the reset signal are asserted continues for a first period of time or longer. The host controller generates a first interrupt signal for starting a first driver in response to the detection of the occurrence of the error. The first driver, when started by the first interrupt signal, changes the operation mode of the memory card from the second operation mode to a first operation mode by controlling the host controller.

Host apparatus and memory system

According to one embodiment, a memory system, such as a SDIO card, includes a nonvolatile semiconductor memory device, a control section, a memory, an extended function section, and an extension register. The extended function section is controlled by the control section. A first command reads data from the extension register in units of given data lengths. A second command writes data to the extension register in units of given data lengths. A extension register includes a first area, and second area different from the first area, information configured to specify a type of the extended function and controllable driver, and address information indicating a place to which the extended function is assigned, the place being on the extension register, are recorded in the first area, and the second area includes the extended function.

Memory system in which extended function can easily be set

A storage device includes a semiconductor memory storing data. A controller instructs to write data to the semiconductor memory in accordance with a request the controller receives. A register holds performance class information showing one performance class required to allow the storage device to demonstrate best performance which the storage device supports, of performance classes specified in accordance with performance.

Growing community of inventors

Fussa, Japan

Akihisa Fujimoto