Fujitsu Corporation

Fujitsu Microcomputer Systems Limited

Fujitsi Limited

Akihiro Yoshitake

Hideyuki Iino

Toshiharu Ohshima

Hidenori Hida

Chikaaki Kodama

Toshiharu Ohashima

A layer defining unit defines different layer numbers to oblique wiring diagrams and via cell diagrams which are included in layout data of a semiconductor integrated circuit design. A first diagram blending unit fetches diagram data including the oblique wiring diagrams and the via cell diagrams from the layout data, synthesizes the diagrams every same layer number, and blends them in overlapped portions. An oblique wiring verifying unit verifies an interval between the oblique wiring diagrams blended by the first diagram blending unit by an allowable minimum interval value S. A second diagram blending unit synthesizes the verified oblique wiring diagram and the via mat diagram of the via cell, thereby forming an oblique wiring mask diagram blended in an overlapped portion. A blended diagram verifying unit verifies an interval between the oblique wirings having projecting portions by the via cells of the oblique wiring mask diagram blended by the second diagram blending unit by an allowable minimum interval value T (where, T&#x3c;S).

Wiring diagram verifying method, program, and apparatus

The invention provides a clock distribution circuit which can be applied readily also to a chip (semiconductor integrated circuit) of the building block type and can realize reduction in skew. The clock distribution circuit includes a first buffer disposed at a central location of the chip for receiving an output of an input driver, four second buffers individually disposed at central locations of four sides of the chip for receiving an output of the first buffer, a plurality of third buffers for receiving outputs of the second buffers, and a last stage connection wiring line system for connecting all of outputs of the third buffers commonly to extract a clock signal to be supplied to clock terminals. The third buffers are disposed on linear lines parallel to the two upper and lower sides of the chip, and the outputs of the third buffers are connected to each other by linear wiring lines. The clock distribution circuit further includes a load adjustment structure for adjusting a load to the first buffer or/and each of the second buffers. The present invention can be applied to a chip of the building block type which includes a RAM or a large number of huge macro blocks and the like.

Clock distribution circuit for semiconductor integrated circuit

A data processor decoding and executing a train of instructions of variable length. The data processor includes a first instruction control means for temporarily storing a prefetched instruction code and sequentially outputting said instruction code with units of a predetermined number of bits, and a second instruction control means for decoding an instruction code fed from the first instruction control means, generating control information for data processing based on the decoding, and outputting data indicating instruction update demand quantity to the first instruction control means. Based on the data indicating the update demand quantity, the first instruction control means judges whether it has output a valid instruction code of length exceeding the update demand quantity, and provides an indication of validity or invalidity of the decoded instruction code and controls updating of the instruction code based on a result of the judgement. As a result, it becomes possible to reduce time necessary for the supply of instruction codes and thus improve a data processing speed as the entire processor.

Data processor decoding and executing a train of instructions of

Microprocessor having a variable length instruction format

A data processor decoding and executing a train of instructions including a plurality of sets of an instruction code field and a corresponding addressing field. The data processor includes a decoding unit for decoding the instruction code field and the corresponding addressing field, and outputting an instruction tag information and an addressing information, respectively, in response to a control signal generated at a predetermined frequency; a holding unit for holding the addressing information fed from the decoding unit, and outputting a holding result in response to the control signal; and a detecting unit responsive to the instruction tag information, addressing information and holding result. The detecting unit effects a judgement of whether the instruction tag information indicates that it is an instruction to check undefined addressing of the addressing field decoded in the preceding stage or in the present stage, and detects the undefined addressing based on a result of the judgement. As a result, it becomes possible to check undefined addressing prescribed for each instruction without lowering instruction execution performance of the data processor.

System for checking undefined addressing prescribed for each instruction

A direct memory access (DMA) controller is adaptable to control a DMA which is independently made in a plurality of channels of a data processing apparatus, where the plurality of channels have predetermined priority sequences and the DMA controller includes a bus and terminal controller coupled to a system bus for obtaining a right to use the system bus responsive to a transfer request, an interrupt and slave controller coupled to the system bus for controlling an interrupt which is made to a central processing unit (CPU) when a data transfer ends for each of the plurality of channels and for controlling an access from the CPU, and an operation determination part for determining an operation of the DMA controller depending on the transfer request, whether or not the bus and terminal controller obtained the right to use the system bus and whether or not the access is made from the CPU. The slave and interrupt controller includes an interrupt controller for supplying to the CPU an interrupt of a channel in which an abnormal end of a data transfer has occurred with a priority over other channels in which a normal end of a data transfer has occurred regardless of the priority sequences of the plurality of channels.

Direct memory access controller with expedited error control

A semiconductor integrated circuit device includes an internal logic circuit for carrying out a logic operation and generating an output signal based on the logic operation, and an output buffer circuit connected to the internal logic circuit, for outputting the output signal through an output terminal in synchronism with a clock signal. The semiconductor integrated circuit also includes a non-overlap clock generator, and a third-clock generator. The non-overlap clock generator generates a first internal clock signal which falls in synchronism with a falling edge of an external clock signal, and generates a second internal clock signal which falls in synchronism with a rising edge of the external clock signal, the internal logic circuit carrying out the logic operation in synchronism with the first and second internal clock signals. The third-clock generator generates a third internal clock which rises in synchronism with the falling edge of the second internal clock signal and which falls in synchronism with the falling edge of the first internal clock signal, the third internal clock being supplied, as the clock signal, to the output buffer circuit.

Growing community of inventors

Kawasaki, Japan

Akihiro Yoshitake