Hitachi, Ltd.

Renesas Technology Corp.

Other

Akihiro Yaguchi

Asao Nishimura

Makoto Kitano

Sueo Kawai

Gen Murakami

Masahiro Ichitani

Junichi Saeki

Hiroshi Kikuchi

Kunihiko Nishi

Kunihiro Tsubosaki

Takashi Yokoyama

Akio Hasebe

Ichiro Anjoh

Hiroshi Hozoji

Takashi Yamazaki

Kazuyoshi Oshima

Aizo Kaneda

Shozo Nakamura

Isamu Yoshida

Hiroyoshi Kokaku

Noriyuki Kinjo

Masatsugu Ogata

Masanori Segawa

Syuuji Eguchi

Ichiro Anjo

Ryuji Kohno

Hideo Miura

Tetsuro Matsumoto

Naotaka Tanaka

Tetsurou Matsumoto

Nae Yoneda

Atsushi Kazama

Tetsuo Kumazawa

Akira Nagai

Hideki Tanaka

Ichio Shimizu

Ryo Haruta

Junichi Arita

Shuji Eguchi

Mamoru Mita

Mitsuaki Haneda

Takeshi Terasaki

Hiromichi Suzuki

Toshiya Satoh

Masahiko Ogino

Satoshi Nakamura

Tatsuya Nagata

Takao Miwa

Akihiko Iwaya

Tadanori Segawa

Maya Obata

Masayoshi Tsugane

Chikako Kitabayashi

Masachika Masuda

Hiroyuki Ohta

Takahiro Daikoku

Nobuo Owada

Norio Ishitsuka

Shigeki Hirasawa

Takumi Ueno

Kazuo Yamazaki

Akio Hoshi

Naozumi Hatada

Toshio Hattori

Toshio Hatsuda

Toshihiro Yasuhara

Chikako Imura

Toshinori Ozaki

Souji Sakata

Kouta Nagano

Kiyomi Kojima

In a production of a semiconductor device, after a step in which a thermosetting resin is thermally cured to seal a semiconductor chip with the resin and before a step in which a characteristic of the semiconductor chip is inspected, the thermosetting resin is baked at a temperature higher than the resin sealing temperature in said resin sealing step.

Method for manufacturing semiconductor device

A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The distance between farthest ones of external terminal positioned at an outermost end portions of said second semiconductor chip is smaller than that of the first semiconductor chip.

Multi-chip module

A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

In a small semiconductor device having external terminals on a semiconductor element and a semiconductor module mounted with the small semiconductor device, disconnection of the external terminals is prevented when a temperature change occurs under the conditions that the semiconductor device is mounted on a printed circuit board. To achieve this a projection is formed on a land which is an external terminal bonding area of the semiconductor device, and a protruded portion of the projection is bonded to the external terminal. An intervening portion of a protective film made of resin material is formed between the lands and semiconductor element.

Semiconductor device provided with rewiring layer

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the 'Lead-On-Chip' or 'Chip-On-Lead' structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Semiconductor device

A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bonded to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.

Semiconductor device and lead frame therefor

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the &ldquo;Lead-On-Chip&rdquo; or &ldquo;Chip-On-Lead&rdquo; structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

A small semiconductor device which can be fabricated at the wafer level has high reliability of external terminals with respect to distortion caused by differential thermal expansion between a semiconductor element of the device and a printed circuit board and has superior electrical performance achieved through reduced static capacitance of interconnections. A thick stress-moderating layer with a low elastic modulus is interposed between the semiconductor element and interconnections and lands and improves the reliability of external terminals by absorbing distortion caused by the differential thermal expansion. The thick stress-moderating layer also reduces static capacitance between the interconnections and internal interconnections of the semiconductor element. Even around element electrodes, where the stress-moderating layer is not formed, static capacitance is reduced by an insulating film interposed between the interconnections and the semiconductor element.

Semiconductor device and mounted semiconductor device structure

A miniature semiconductor apparatus is outstanding in reflow resistance, temperature cycle property, and PCT resistance corresponding to high density packing, high densification, and speeding up of processing. The semiconductor apparatus has at least one stress cushioning layer on a semiconductor element with an electrode pad formed, having a conductor on the stress cushioning layer, having a conductor for conducting the electrode pad and conductor via a through hole passing through the stress cushioning layer between the electrode pad and the conductor, having an external electrode on the conductor, and having a stress cushioning layer in an area other than the area where the external electrode exists and a conductor protection layer on the conductor, wherein the stress cushioning layer includes crosslinking acrylonitrile-butadiene rubber having an epoxy resin which is solid at 25&deg; C. and a carboxyl group.

Semiconductor apparatus having stress cushioning layer

In a ball grid array type semiconductor device mounted on a printed wiring board, the external terminals can be prevented from being broken down even when the ambient temperature on the device is repeatedly changed. A flexible adhesive member for gluing the semiconductor chip to an insulating tape is provided to cover up to a region including the lands to which the external terminals are bonded and which are provided on the insulating tape surface. The flexible adhesive member for covering the lands may be replaced by a flexible low-elasticity member.

A semiconductor device which can improve the connection reliability of solder bumps and productivity in manufacturing. Insulating tape having wiring patterns on its surface is bond ed to a lead frame. Semiconductor elements are loaded and circuit formed surfaces and sides of the semiconductor elements are sealed with sealing resin. After arrangements of individual semiconductor devices are formed, the lead frame is separated into individual metal plates to form individual semiconductor devices. Such simultaneous production of a plurality of semiconductor devices enhances productivity, and improves flatness of the insulating tape, whereby the connection reliability of solder bumps is improved.

A small semiconductor device close in size to a semiconductor chip which prevents warping of semiconductor chips or wafer and delamination of an interface from an interlayer insulating film, both caused by thermal stresses of a rewiring layer. The use of a Cu composite alloy containing 80 vol. % or less of Cu O, which alloy has a smaller linear thermal expansion coefficient and a smaller elastic modulus than those of pure copper, as a main material of the rewiring layer can reduce the thermal stresses in the rewiring layer, realizing a semiconductor device in which warping of semiconductor chips or wafer and delamination of layers will not easily occur.

Growing community of inventors

Tsuchiura, Japan

Akihiro Yaguchi