Hitachi, Ltd.

Akihiro Takamura

Yoshio Miki

Hiroaki Fujii

Tatsuya Kawashimo

A construction of the present invention includes a procedure of setting in advance a storing area in a converted instruction storing area table for recording a corresponding relation between a program before conversion and a storing address of a converted program at an initialization processing portion of an emulation program. In setting the storing area, address information on a memory on a portion whose execution frequency is high upon an emulation operation is acquired, and an address that brings about cache conflict on an instruction cache with the portion whose execution frequency is high is excepted and set as an area to store therein a converted instruction.

Memory management method for dynamic conversion type emulator

A hierarchical server system efficiently balances the processing load thereon and for shortening the processing time therein is provided, such as a web server system. A system controller, a load balancing device, and a shared memory are provided in a multi-layer server system made of a plurality of servers. When processing implemented with a first layer server is temporarily stopped in order to acquire information needed for processing from a second layer server, process information needed to resume the processing is recorded in the shared memory. When the necessary information is sent back to the first layer server, the system controller inquires about work statuses of all first layer servers to select another first layer server to resume the processing based upon the inquiry results. The then selected first layer server then resumes the processing using the information that was sent back and the process information in the shared memory.

Hierarchical server system

A main logical unit and a standby logical unit are defined by a process controller in a shared main memory multiprocessor, and an information storage space accessible from both logical units is provided. The main logical unit stores address information onto that information storage space by indicating a memory area it controls as the main memory area. When failover or cloning becomes necessary, the standby logical unit searches the information on the applicable address. Then from the applicable information, it also searches information on the main memory area controlled by the main logical unit to establish in itself and forms a processing environment and state identical to the main logical unit such that the standby logical unit takes over all or a portion of the processing of the main logical unit. This enables the construction of a server system of high operability to overcome failures and poor response times by failover and cloning, etc.

Server system operation control method

A processor having an execution result prediction function for an instruction that performs a branch/value prediction by which a high percentage of correct predictions can be realized ought to be provided. Accordingly, in a branch/value prediction circuit having a set associative, a priority of an entry used for a prediction is increased only when an execution result is referred to for the prediction and the prediction is correct, and the execution result is registered in the entry of the lowest priority when the execution result for the instruction is newly registered in a history table. Thus, the entry of a low percentage of correct predictions becomes easy to erase and prediction accuracy can be increased by updating the priority only when the prediction is correct.

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Koganei, Japan

Akihiro Takamura