Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Otsuka Pharmaceutical Company, Limited

Kikusui Seisakusho Ltd.

Akihiro Sawada

Hironori Akamatsu

Masashi Agata

Shunichi Iwanari

Hirohito Kikukawa

Hisakazu Kotani

Toshio Yamada

Ichiro Nakao

Hiroyuki Yamauchi

Shohei Yamada

Tomohiro Kakitani

Kazuhiro Matsuyama

Yuji Tsujiura

Seiichiro Yoshida

Shinshu Unida

An internal substance supplier includes a conveying mechanism including a conveying member configured to capture and convey an internal substance, and a supply mechanism including a scraping member disposed to cross a conveyance route of the substance by the conveying member in the conveying mechanism and configured to collide with the substance conveyed by the conveying member, a gliding member including a recessed groove configured to guide the substance colliding with the scraping member and scraped from the conveying member, to be adjacent to a position vertically above a die bore in a table in a compression-molding machine, and a push transfer member including a projection configured to come into contact with the substance, push the substance to a start edge of the recessed groove in the gliding member, and move along the recessed groove to transfer the substance to an end edge of the recessed groove.

Internal substance supplier and method of producing molded product

In a PLL circuit including a VCO having a plurality of oscillation frequency bands, a TDC circuit calculates a phase difference between a predetermined reference signal from a fixed frequency divider and a PLL frequency-divided signal from a variable frequency divider. The TDC circuit detects the amount of time by which the phase of the PLL frequency-divided signal leads or lags with respect to that of the reference signal in one cycle of the reference signal, thereby detecting which of the signals has a higher frequency and which has a lower frequency. Therefore, for each oscillation frequency band, the frequency comparison is completed in one cycle of the reference signal, allowing an oscillation frequency band selection circuit to detect an optimum oscillation frequency band corresponding to a predetermined PLL output frequency in a short time.

Phase locked loop circuit and wireless communication system

A PLL frequency synthesizer is provided with a linearization circuitwhich receives an oscillation frequency control signal Vfrom a loop filter LF. The linearization circuitoutputs a charge pump current control signal CP, depending on a potential level of the oscillation frequency control signal V. The larger the value of the charge pump current control signal CP, the higher the potential level. A charge pump CP receives the charge pump current control signal CP, and causes a current corresponding to the value to flow in or out. Therefore, with a simple circuit structure, loop gain characteristics of the PLL frequency synthesizer can be regulated to be constant. Therefore, even when a variable capacitance element incorporated in a voltage control oscillator has nonlinear characteristics with respect to the potential of the input oscillation frequency control signal, the loop gain characteristics of the PLL frequency synthesizer having the voltage control oscillator can be regulated to be constant.

PLL frequency synthesizer

In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Data transmission circuit, data line driving circuit, amplifying

Semiconductor integrated circuit with a data transmission circuit

In a synchronous DRAM required to be capable of performing high-speed consecutive operations in synchronism with a clock signal, a DBI-line pair is connected between a DQ-line pair and an RDB-line pair, and pipeline operation whose single cycle time is divided into four periods is employed. This S-DRAM has following: a first precharge circuit for precharging or voltage-equalizing the DQ-line pair to a power supply voltage level in the first and forth periods only; a second precharge circuit for voltage-equalizing the DBI-line pair to a ground voltage level in the first and second periods only; a third precharge circuit for voltage-equalizing the RDB-line pair to the power supply voltage level in the first and second periods only; first and second differential amplifiers for transmitting data on the DQ lines onto the DBI lines in the third period and for holding the data on the DBI lines in the fourth period; and a third differential amplifier which transmits the data on the DBI lines onto the RDB lines in the third period and which holds the data on the RDB lines in the fourth period.

Semiconductor memory device

N-piece redundant address comparing circuits are individually composed of impedance converting circuits, so that information using redundancy is transmitted as an impedance value. Consequently, even though the N becomes larger as the capacity of a memory becomes larger, a signal line having large capacitance and the node of a redundant judging circuit are not charged or discharged. A high-speed operation can be realized without being affected by the capacitance of the signal line or by the capacitance of the node of the redundant judging circuit.

Semiconductor integrated circuit

An external power supply voltage V.sub.CC is applied to a peripheral circuit as a first internal power supply voltage V.sub.PERI. A power supply voltage control circuit outputs a voltage control signal V.sub.SIG of a high logic level if V.sub.CC is not greater than a low limit voltage V.sub.0L in a voltage range specified by VCC recommended operating conditions, otherwise it outputs V.sub.SIG of a low logic level. A power supply circuit applies a second internal power supply voltage V.sub.W and a third internal power supply voltage V.sub.WORD to a memory cell section. V.sub.W is equal to V.sub.PERI if V.sub.SIG is HIGH, while on the other hand V.sub.W is a voltage as a result of boosting V.sub.PERI. V.sub.WORD is a voltage as a result of boosting VW to a further extent. A row decoder sends out V.sub.W onto an enable signal line of a row of sense amplifiers, and V.sub.WORD onto a word line of a memory cell array so that V.sub.W becomes a high-logic-level data write voltage to a memory cell. This adequately prolongs the data-holding time with no sacrifice in memory cell voltage resistance.

Semiconductor memory device having a prolonged data holding time

In a semiconductor memory having a redundant circuit, a plurality of first normal cells and a plurality of first spare cells are connected to a first pair of data lines, and a plurality of second normal cells and a plurality of second spare cells are connected to a second pair of data lines. Both pairs of data lines are connected to an output data line through a selecting amplifier. A normal cell is selected based on a combination of NGWL1, NGWL2, . . . with BLK1, BLK2, both NGWL1, NGWL2, . . . and BLK1, BLK2 being supplied from a decoder, and a spare cell is selected based on a combination of the BLK1, BLK2 supplied from the decoder with SGWL1, SGWL2, . . . supplied from a redundancy judging circuit. A second spare cell is selected when a first normal cell is selected, and a first spare cell is selected when a second normal cell is selected. Only at the time when a spare address is entered, one of the SGWL1, SGWL 2, . . . is raised. This not only achieves a high-speed reading and a high defect-relief rate, but also reduces the current consumption and the chip area.

Growing community of inventors

Osaka, Japan

Akihiro Sawada