Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Akihiro Matsumoto

Hideo Nishimatsu

In a semiconductor memory device of a multiple-output port type including a plurality of read buses, data in a write bus are sequentially written into write registers, and the thus written data are transferred to the even-numbered bit-line pairs of a memory cell array section, and then data are again written into the write registers, after which the thus written data are transferred to the odd-numbered bit-line pairs. Then, the data in the even-numbered bit-line pairs are transferred to read A registers which correspond to one of the read buses, and the thus transferred data are sequentially read into the read bus, and thereafter, the data in the odd-numbered bit-line pairs are transferred to the read A registers and the thus transferred data are sequentially read into the read bus. Thus, the total number of read registers corresponding to all the read buses is made equal to that of the bit-line pairs, and is accordingly smaller as compared with a conventional semiconductor memory device. This allows all the read registers to be aligned along the same lane, so that the entire memory chip can be made smaller in size.

Semiconductor memory device and control method for the same

A memory includes a memory cell array unit, a plurality of memory cell bit lines connected to the memory cell array unit, a plurality of column selecting gates, and a plurality of sub data lines connected to the memory cell bit lines via the column selecting gates. A column selector serves to select and make conductive members of the column selecting gates so that data can be transmitted between successive members of the memory cell bit lines and the sub data lines. The memory further includes N-bit main data lines, where N denotes a given natural number. In addition, the memory includes data line selecting gates. The sub data lines are connected to the main data lines via the data line selecting gates. A data line selector serves to select and make conductive members of the data line selecting gates so that data can be transmitted between N successive members of the sub data lines and the main data lines.

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Osaka, Japan

Akihiro Matsumoto