Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Other

Akihiro Matsuda

Toru Nasu

Eiji Fujii

Yoshihisa Nagano

Yasuhiro Uemoto

Koji Arita

Atsuo Inoue

Yasuhiro Shimada

Tatsuo Otsuki

Taketoshi Matsuura

Koji Akiyama

Masaaki Yamauchi

Takashi Aoki

Tooru Nasu

Tatsuo Ootsuki

Carlos Alberto Paz De Araujo

Shinitirou Hayashi

Koichi Arita

Masaki Kibe

Takumi Mikawa

Joseph D Cuchiaro

Jolanta Bozena Celinska

Koji Aoto

Keisuke Tanaka

Toshie Kutsunai

Toyoji Ito

Yasufumi Izutsu

Jeffrey W Bacon

Keisaku Nakao

Larry D McMillan

Hideo Nagai

Tatsuo Morita

Shinichiro Hayashi

Michael C Scott

Masamichi Azuma

Gota Kano

Fumio Sakamoto

Yoshio Yamaguchi

Kenji Date

Yoshihiro Shimada

In the aging process performed by applying a voltage having an alternating voltage component between a scan electrode and a sustain electrode, an erase discharge occurs in succession to an aging discharge. According to the aging method, an erase discharge-suppressing voltage is applied to at least any one of the scan electrode, the sustain electrode, and the data electrode. Although the erase discharge repeatedly occurs in the wake of the aging discharge, the erase discharge-suppressing voltage suppresses the ones that occur when the scan electrode has voltage level higher than the sustain electrode.

Aging method of plasma display panel

In an aging process in which a voltage having an alternate voltage component is applied to at least between a scan electrode and a sustain electrode so as to form a discharge dent (sputter dent) on a protecting layer, the aging discharge dent is formed so as to satisfy any one of the following. First, the discharge dent on the scan electrode-side has a width which is narrower than the discharge dent on the side of sustain electrode. Second, the discharge dent on the side of sustain electrode is formed so that the depth of the discharge dent in the area away from a scan electrode paired with a sustain electrode as a display electrode is shallower than the depth of the discharge dent in the area close to counterpart scan electrode.

Plasma display panel and method of aging the same

A plasma display panel is provided that includes scan electrodes, sustain electrodes, and address electrodes. A first pulse voltage for the address electrodes or a second pulse voltage for the address electrodes is applied to the address electrodes in an aging step in which aging discharge is performed by alternately applying pulse voltage for the scan electrodes and pulse voltage for the sustain electrodes at least across the scan electrodes and the sustain electrodes. The first pulse voltage has a rising edge timing synchronized with a rising edge timing of the pulse voltage for the scan electrodes and a pulse width smaller than that of the pulse voltage for the scan electrodes. The second pulse voltage has a rising edge timing synchronized with a rising edge timing of the pulse voltage for the sustain electrodes and a pulse width smaller than that of the pulse voltage for the sustain electrodes.

Method of manufacturing plasma display panel

Plasma display panel and its aging method

Disclosed is a method of manufacturing plasma display panels for carrying out aging with high productivity. In an aging process for applying a predetermined voltage and driving plasma display panelsfor display operation, each plasma display panel is set into an aging unit provided with cooling means, and the aging is carried out on the plasma display panel while cooling the plasma display panel by the cooling means provided in the aging unit. This method can thus reduce temperature rise of the panel and prevent the panel from being cracked during the aging process.

Method for manufacturing plasma display panel

The semiconductor device of the invention includes a capacitor device, which is formed on a substrate and which includes a capacitive lower electrode, a capacitive insulating film made of an insulating metal oxide film and a capacitive upper electrode. An interlevel insulating film having an opening reaching the capacitive upper electrode is formed over the capacitor device. A metal interconnection including a titanium film is formed over the interlevel insulating film so as to be electrically connected to the capacitive upper electrode through the opening. An anti-diffusion film having conductivity is formed between the capacitive upper electrode and the metal interconnection for preventing titanium atoms composing the titanium film of the metal interconnection from passing through the capacitive upper electrode and diffusing into the capacitive insulating film.

Semiconductor device and method for fabricating the same

A precursor for forming an aluminum oxide film comprises a liquid solution of an aluminum organic precursor compound in an organic solvent. In a second embodiment, the precursor comprises a suspension of aluminum oxide powder in a solution of an aluminum organic precursor compound. A precursor according to the invention is deposited on a substrate by dipping, rolling, spraying, misted deposition, spin on deposition, or chemical vapor deposition then heated to fabricate transparent aluminum oxide films. The electronic properties of the aluminum oxide films may be improved by depositing a plurality of layers of the precursor and annealing the precursor between layers.

Liquid precursors for aluminum oxide and method making same

A Ti/TiN adhesion/barrier layer is formed on a substrate and annealed. The anneal step is performed at a temperature within a good morphology range of 100&deg; C. above a base barrier anneal temperature that depends on the thickness of said barrier layer. The base barrier anneal temperature is about 700&deg; C. for a barrier thickness of about 1000 &angst; and about 800&deg; C. for a barrier thickness of about 3000 &angst;. The barrier layer is 800 &angst; thick or thicker. A first electrode is formed, followed by a BST dielectric layer and a second electrode. A bottom electrode structure in which a barrier layer of TiN is sandwiched between two layers of platinum is also disclosed. The process and structures also produce good results with other capacitor dielectrics, including ferroelectrics such as strontium bismuth tantalate.

Integrated circuit capacitors with barrier layer and process for making the same

A semiconductor device forming a capacitor through an interlayer insulating layer on a semiconductor substrate on which an integrated circuit is formed. This semiconductor device has an interlayer insulating layer with moisture content of 0.5 g/cm,or less, which covers the capacitor in one aspect, and has a passivation layer with hydrogen content of 10,atoms/cm,or less, which covers the interconnections of the capacitor in other aspect. By thus constituting, deterioration of the capacitor dielectric can be prevented which brings about the electrical reliability of the ferroelectric layer or high dielectric layer.

Semiconductor device having a capacitor exhibiting improved moisture resistance

The present invention provides a semiconductor device including a semiconductor element and a dummy semiconductor element adjacent to the semiconductor element. When the semiconductor element is a capacitor element including a bottom electrode, a top electrode and a dielectric layer between the electrodes, a dummy capacitor element also has dummy electrodes and a dummy dielectric layer between the dummy electrodes. The dummy electrode is located so that a space between the top electrode of the capacitor element ad the dummy top electrode is in a predetermined range (e.g. 0.3 &mgr;m to 14 &mgr;m). The dummy capacitor element prevents the capacitor dielectric layer from degrading since the collision of the etching ions with the capacitor dielectric layer in a dry etching process is suppressed.

Semiconductor device having a ferroelectric TFT and a dummy element

Semiconductor device having capacitor and manufacturing method thereof

Semiconductor capacitive device having improved anti-diffusion properties and a method of making the same

Metal organic precursor compounds are dissolved in an organic solvent to form a nonaqueous liquid precursor. The liquid precursor is applied to the inner envelope surface of a fluorescent lamp and heated to form a metal oxide thin film layer. The metal oxide thin film layer may be a conductor, a protective layer or provide other functions. The films have a thickness of from 20 nm to 500 nm. A conductive layer comprising tin-antimony oxide with niobium dopant may be fabricated to have a differential resistivity profile by selecting a combination of precursor composition and annealing temperatures.

Fluorescent lamp and method of manufacturing same

Semiconductor device having a passivation layer which minimizes diffusion of hydrogen into a dielectric layer

A method of manufacturing a capacitor comprises a step of forming a first dielectric layer composed of a ferroelectric material or a dielectric material possessing high permittivity on a first electrode, a step of sintering the first dielectric layer, a step of forming a second dielectric layer on the first dielectric layer, and a step of forming a second electrode on the second dielectric layer. By forming the second dielectric layer having small crystal grain size on the first dielectric layer having large crystal grain size, the surface of the capacitor insulating layer becomes flat.

Method of manufacturing capacitor included in semiconductor device and

Growing community of inventors

Osaka, Japan

Akihiro Matsuda