Kabushikikaisha Kenwood

Other

Leader Electronics Corporation

Jvc Kenwood Corporation

Akihiro Horii

Kenichi Shiraishi

Shoji Matsuda

Soichi Shinjo

Akinori Hashimoto

Hisakazu Katoh

Tomohiro Saito

Fumiaki Minematsu

Shoichi Suzuki

Shigeyuki Itoh

Kazuhiko Shibuya

Yuichi Iwadate

Ryuichi Okazaki

Susumu Nishijima

Shoji Matuda

Kenichi Ishihara

Masaki Miyamoto

Takanori Fujii

Tomokazu Nakajima

Hiroshi Okamura

Takahiro Wada

Hirosi Okamura

A digital satellite broadcast receiver capable of an optimum signal reception even when an arbitrary outdoor unit is connected. Please noise characteristics of an outdoor unit connected to a digital satellite broadcast receiver when receiving a burst symbol is estimated based on a bit error rate of an 8PSK modulation signal determined by a trellis decoder () when a CNR measured by a CNR measurement circuit () is equal to a preset value, and, based on the estimated phase noise characteristics of the outdoor unit, a filter factor of a loop filter () inserted into a carrier regenerative loop is set.

Radio digital signal receiver

A site diversity method, a digital satellite broadcast receiving method and a digital satellite broadcast receiver are provided which can make a difference of data output timing between a main station and a subsidiary station at the time of site exchange as small as possible and can perform re-synchronization as soon as possible. In the site diversity method for digital satellite broadcast, when a site exchange execution designation signal is received, the site is exchanged during a period of a TMCC information field of a predetermined specific frame of a super frame determined when the execution designation signal is received. On the receiver side, information of broadcast is continuously received by detecting a TMCC information field in a specific frame during a period of which field the site was exchanged and by establishing re-synchronization by using a super frame sync pattern Wor Wafter the detected TMCC information field.

Site delivery method, method for receiving digital satellite broadcast, and receiver for digital satellite broadcast

A digital broadcast receiver capable of adequately receiving a higher-level layer service along with a lower-level layer service even if the reception CNR degrades. A demodulation decoding section () of the receiver judges on the basis of transport and multiplexing configuration control information whether the TS packet allocated to each slot is adapted to a higher-level layer service or a lower-level layer service and informs a code writing section () of the result. The code writing section () writes, in each TS packet, a layer identification code for judging whether the TS packet is adapted to a higher-level layer service or a lower-layer service and synthesizes a resultant TS packet. A stream separating section () reads the layer identification code along with the PID in the packet header included in the TS packet and finds and extracts a desired TS packet.

Digital broadcast receiver and digital broadcast receiving method

An improved apparatus for receiving BS digital broadcast is disclosed. The apparatus for receiving BS digital broadcast of the present invention has first to third filters and a selective complex calculator circuit. Each of the first to third filterstoidentifies the modulation technique applied to the received signal, by the modulation identification signals A, Areceived from a timing generator circuit, and filters a phase error signal PED according to the identified modulation technique. The selective complex calculator circuitshifts the phase of a signal point indicated by an I signal ADIand a Q signal ADQabsolute-phased by an absolute-phasing sectionby a phase corresponding to the phase error signal filtered by the first to third filtersto. At this moment, the selective complex calculator circuitselects the phase error signal corresponding to the modulation technique identified from the modulation identification signals A, Areceived from the timing generator circuit. Consequently, in the burst receiving, it is possible to reduce the effect on the error rate because of the signal noise of the ODU to a degree equal to that in the continuous receiving.

Apparatus and method for receiving BS digital broadcast

Frame synchronization is quickly established to acquire an RF channel in a short time. Numerically controlled oscillators-to-, complex calculation circuits-to-, band limit filters-to-, a selector, a phase error detection circuit, a loop filter, and an AFC circuitcompose a carrier regeneration loop for removing the frequency error of the carrier included in an in-phase component I and a quadrant component Q of the baseband signal input to the complex calculation circuits-to-. A timing generatordetects which of frame synchronization pattern detection circuits-to-has detected a frame synchronization pattern, provides the selectorwith a selection signal corresponding to the decision result, and sends a switch signal to the AFC circuit. Thereafter, the carrier for removing the frequency error included in the baseband signal is regenerated to acquire an RF channel in a short time.

Method and circuit for acquisition

A demodulator having an improved reliability of the decoding of a TMCC signal is used for digital broadcasting receivers for receiving digital broadcasting by layered transmission system. A pseudo-pattern generator () generates fixed pseudo-data which involves no error with respect to a main signal after a TMCC signal and maintains the convolution relationship, and inserts the pseudo-data between the TMCC signal and the main signal through a selector (B) and a selector (), thereby conducting Viterbi decoding.

Demodulator

A BS digital broadcasting receiver which eliminates the uncertainty of an ODU's phase noise-dependent switching point when switching a receiving system. The receiver is provided with a demodulator circuit (A) having a carrier regenerating circuit (A) based on demodulation data in a BPSK modulation section, and with a demodulator circuit (B) having a carrier regenerating circuit (B) based on demodulation data in each time-division modulation section, wherein, when a lock for carriers regenerated by the carrier regenerating circuit (A) is maintained and carriers regenerated by the carrier regenerating circuit (B) is locked, demodulation data, in the BPSK demodulation section and a QPSK demodulation section, output from the demodulator circuit (A) and 8-PSK-modulated demodulation data output from the demodulator circuit (B) are selected by a selector () for outputting.

BS digital broadcasting receiver

A digital demodulator which will need no absolute phasing circuit is provided. A known-pattern BPSK signal generating circuit generates the same known-pattern BPSK signal as a known-pattern BPSK signal in a received digital modulated wave in synchronism with the known-pattern BPSK signal in the received digital modulated wave, a carrier-reproducing phase error detecting circuit has a phase error table where one of reference phases in a signal point position of a demodulation baseband signal is made a convergence point, a phase error voltage corresponding to a phase error between a phase determined from the signal point position of the demodulation baseband signals and a phase convergence point is sent out, by enable-controlling a carrier-reproducing loop filter according to the known-pattern BPSK signal outputted from the known-pattern BPSK signal generating circuit , the phase error voltage is smoothed, and carrier reproduction is performed while controlling the frequency of a reproduced carrier according to the smoothed output so that the phase in the signal point position coincides with the phase convergence point.

Digital demodulator

A dummy error addition circuit for adding a dummy error to an orthogonal modulation symbol data, wherein a value based on a specified bit error rate is loaded to count clock signals at a counter ( ), a carrier of the counter ( ) stores outputs from a PN data generator ( ) in a shift register ( ), outputs from a PN comparison circuit ( ) when stored data agree with count values of the counter ( ) are recognized as error pulses, a bit selector ( ) randomly selects, on receiving error pulses and based on outputs from a PN data generator ( ), bits to which to add errors in an orthogonal modulation data, e.g. a PSK modulation symbol data, at interval based on a bit error rate, and bits selected from the orthogonal modulation data are inverted in a bit inversion circuit ( ) for outputting to thereby add errors.

Dummy error addition circuit

To provide a de-interleave circuit used for a BS digital broadcasting receiver. The de-interleave circuit is provided with less memory. An address data generator ( ) supplies address data (A) to a de-interleave memory ( ) in a de-interleave order. Each main signal is read from an address location in the de-interleave memory ( ) specified by address data (A), and a following main signal is interleaved and written in that address location of the memory. As a result, the de-interleave memory ( ) only requires space for one superframe.

De-interleave circuit

A digital broadcasting receiver is provided which can reproduce a carrier quickly and capture a desired signal at high speed. A carrier reproduction phase error detection circuit ( ) detects a phase error voltage in accordance with a demodulation output obtained by demodulating a demodulated wave of a modulated wave during a predetermined section in a header section. A peak number calculation circuit ( ) calculates an error frequency between a desired reception frequency and a reproduction carrier frequency in accordance with the phase error voltage. A differential coefficient calculation circuit ( ) calculates the polarity of the error frequency. A step frequency control circuit ( ) converts the calculated error frequency having the calculated polarity into a step frequency width for automatic frequency control. The reproduction carrier frequency is scanned at the converted step frequency width until a frame sync is established after the frame sync is detected. It is therefore possible to reproduce the carrier quickly and capture the desired signal at high speed.

Digital broadcasting receiver

To provide a receiver not requiring any large circuit. A carrier-wave-phase-error table - A for BPSK modulation in which a range equal to or more than 0 of I-axis is defined is prepared for a carrier-wave regenerating circuit A of a demodulating circuit A for orthogonally detecting a received signal in which digital signals according to BPSK, QPSK, and 8PSK modulations are time-multiplexed and outputting I and Q symbol-stream data I and Q for each symbol. When a remapper A outputs I and Q obtained by inversely phase-rotating I and Q by &minus;&THgr; against a received-signal-phase rotation angle &THgr; and generating an absolute phase of I and Q , a phase-error detecting circuit obtains a shift angle &THgr;&prime; up to a target phase convergent angle of a received-signal point shown by I and Q viewed in the positive direction of I-axis according to a modulation system currently demodulated, reads phase error data corresponding to I and Q obtained by phase-rotating I and Q by &minus;(&THgr;&plus;&THgr;&prime;) by the remapper A through time sharing out of the table - A, and corrects a phase of a reference carrier wave so that the phase error data becomes zero.

Receiver

A BS digital broadcast receiver having no 8PSK-demapper and a less number of delay circuits for Trellis encoding. A QPSK baseband signal based upon a reception signal point position of an absolute-phased baseband demodulation signal is Viterbi-decoded by a Viterbi-decoder . An output of the Viterbi-decoder is convolution-reencoded by a convolution encoder . Upper four bits of phase error data are searched from a phase error table for carrier reproduction in accordance with a phase difference between 0 degree and a phase of a phase error detection reception signal point position. The upper four bits are delayed by delay circuits to by a total sum of a time taken to Viterbi-decode and a time taken to convolution-encode. The delayed outputs are demapped by a demapped value conversion circuit A code TCD determined from the demapped output and convolution encode output is output as an MSB of a Trellis 8PSK decode output from an MSB code judging/error detecting circuit

BS digital broadcast receiver

A carrier reproduction circuit which can perform stable carrier reproduction even when reception takes place with low C/N values is provided. The reception phase of the demodulated known-pattern reception signal is detected with a frame synchronizing timing circuit ( ), and based on the detected reception phase, either the phase difference table of absolute phase having one convergence point or the phase difference table of the phase rotated from the absolute phase by 180&deg;, which are included in a carrier reproduction phase difference detecting circuit ( ), is selected, and from the selected phase difference table the output based on the phase difference between the phase obtained from the signal point position of the reception signal and the phase convergence point is obtained, and thus carrier reproduction is implemented by undergoing the reproduced carrier frequency control via an AFC circuit ( ) so that the phase obtained from the signal point position coincides with the phase convergence point.

Carrier reproduction circuit

A small scale circuit can be realized. A timing circuit detects a burst symbol signal period from outputs I and Q of a demodulating circuit A for orthogonally detecting a received signal obtained by time-multiplexing digital signals by BPSK, QPSK, and 8PSK modulation. A pattern regeneration circuit outputs the same PN code pattern as on a transmission side. Inverting circuits and output I, Q as RI, RQ for a bit '0' of a PN code pattern, and &minus;I, &minus;Q as RI, RQ for a bit '1'. A phase error table A contains a phase error between the phase of a received signal point as an output of the inverting circuits and and an absolute phase only for a first quadrant of RI, RQ. A phase error detecting processing circuit A reads the phase error data corresponding to the absolute value of RI, RQ, and adjusts the data into the data depending on the current quadrant of the RI, RQ. A carrier regeneration circuit A amends the phase of a reference carrier for use in orthogonal detection such that an adjusted phase error data indicates zero.

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Zama, Japan

Akihiro Horii