Fujitsu Corporation

Akihiro Hasegawa

Koichi Hashimoto

Masanori Terahara

Hikaru Kokura

Yukinobu Hikosaka

Atsuo Fushida

Takeshi Kamata

Fumihiko Akaboshi

A method of manufacturing a semiconductor device disclosed herein includes: mounting a substrate on an electrostatic chuck placed inside a chamber, the electrostatic chuck having a first temperature and the substrate being retained in advance in an atmosphere having a second temperature lower than the first temperature; fixing the substrate onto the electrostatic chuck by applying a voltage to the electrostatic chuck; heating the electrostatic chuck to a third temperature higher than the first temperature and the second temperature after mounting the substrate; and processing the substrate after the heating.

Method of manufacturing semiconductor device

After an interlayer insulation film () and a CMP stopper film are formed, wiring trenches are formed. Next, after a barrier metal film () and a Cu film () are buried in the wiring trenches, the Cu film () and the barrier metal film () are planarized by CMP or the like until the CMP stopper film is exposed, whereby lower wirings () are formed. Next, the CMP stopper film is removed by dry etching, so that surfaces of the lower wirings () relatively protrude from their surrounding area. Subsequently, an etching stopper film () is formed on the entire surface. Thereafter, via plugs () are formed, and upper wirings () are further formed in the same manner as the lower wirings ().

Semiconductor device and manufacturing method thereof

A method of manufacturing a semiconductor device including the steps of: (a) transporting a semiconductor wafer into a plasma process system, the semiconductor wafer having a semiconductor layer, a field insulating film and a gate insulating film formed on the semiconductor layer, said gate insulating film having a breakdown voltage of B (V) and a thickness of 10 nm or thinner, a conductive layer of a structured antenna formed on the gate insulating film and the field insulating film, the conductive layer having an antenna ratio of 500 or higher, and an insulating material pattern formed on the conductive layer, the insulating material pattern having an opening with an aspect ratio larger than 1; and (b) processing the semiconductor wafer in plasma having an electron temperature of Te (eV) equal to or less than B. With this method, it is possible to prevent damages to a gate insulating film even during a fine pattern process.

Plasma processing with less damage

Growing community of inventors

Nagoya, Japan

Akihiro Hasegawa