Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Toshiba Medical Systems Corporation

Akihiro Goryu

Hiroshi Ohno

Kenji Hirohata

Mitsuaki Kato

Akira Kano

Tomoaki Inokuchi

Yusuke Kobayashi

Tatsuya Nishiwaki

Ryohei Gejo

Hiro Gangi

Tsuyoshi Kachi

Yasuko Fujisawa

Kazumasa Arakita

Satoshi Wakai

Junichiro Ooga

Takahiro Omori

Yoshihiro Ikeda

Hiroya Kano

Shigeo Kaminaga

Shotaro Baba

Tetsuya Kugimiya

Takuya Hongo

Hiroki Nemoto

Hideaki Okano

Tomoya Fumikura

According to one embodiment, a semiconductor device includes first to third electrodes, a conductive member, a semiconductor member, and an insulating member. The conductive member includes a conductive member end portion and a conductive member other-end portion. The conductive member end portion is between the first electrode and the conductive member other-end portion. The conductive member is electrically connected with one of the second electrode or the third electrode. The semiconductor member includes first to third semiconductor regions. The first semiconductor region includes first and second partial regions. The first partial region is between the first and second electrodes. The second semiconductor region is between the first partial region and the third semiconductor region. The third semiconductor region is electrically connected with the second electrode. A portion of the insulating member is between the semiconductor member and the third electrode and between the semiconductor member and the conductive member.

Semiconductor device

A semiconductor deviceincludes a pair of electrodesand a conductive connection memberelectrically bonded to the pair of electrodes. At least a portion of a perimeter of a bonding surfaceof at least one of the pair of electrodesand the conductive connection memberincludes an electromigration reducing area

Semiconductor device and inspection device

According to one embodiment, a semiconductor device includes first to third electrodes, a first conductive member, a semiconductor member, and a first insulating member. The third electrode includes a third electrode end portion and a third electrode other-end portion. The first conductive member includes a first conductive member end portion and a first conductive member other-end portion. The first conductive member is electrically connected with one of the second electrode or the third electrode. The semiconductor member includes first to fourth semiconductor regions. The first semiconductor region includes first and second partial regions. The third semiconductor region is electrically connected with the second electrode. The fourth semiconductor region is electrically connected with the first electrode. At least a portion of the first insulating member is between the semiconductor member and the third electrode and between the semiconductor member and the first conductive member.

A semiconductor device inspection apparatus according to embodiments comprises: an action unit that generates an internal stress in a predetermined direction in a semiconductor device; a stress controller that controls a magnitude of the internal stress generated in the semiconductor device by the action unit; a probe electrically connected to the semiconductor device; a probe controller that supplies a current to the semiconductor device via the probe; and a controller that screens the semiconductor device based on a first current flowing through the semiconductor device via the probe while the internal stress is not generated in the semiconductor device and a second current flowing through the semiconductor device via the probe while the action unit generates the internal stress in the semiconductor device.

Semiconductor device inspection apparatus, semiconductor device inspection method, program thereof, semiconductor apparatus, and manufacturing method therefor

An inspection device comprises: a detecting unit that is connected to a plurality of semiconductor chips having mutually different rates of change of electrical resistance with respect to stress loading direction, and that detects an electrical resistance value of each semiconductor chip from electric current flowing in each semiconductor chip; a first memory unit that is used to hold model data meant for converting an electrical resistance value into a characteristic value indicating at least either temperature, or stress, or strain; a converting unit that converts the electrical resistance value of each semiconductor chip as detected by the detecting unit into the characteristic value using the model data held in the first memory unit; and a second memory unit that is used to store the characteristic value, which is obtained by conversion by the converting unit, as time-series data for each of the plurality of semiconductor chips.

Inspection device, inspection system, intelligent power module, inspection method, and computer program product

A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.

Semiconductor storage device, method of controlling semiconductor storage device, computer program product, and method of fabricating semiconductor storage device

According to an embodiment, in a semiconductor device, a total value of a change amount of chemical potential of the semiconductor device with respect to a expansion direction of a stacking fault and the stacking fault energy of the stacking fault is zero or more.

Semiconductor device and method of manufacturing semiconductor device

A semiconductor device comprises a semiconductor chip and a mounting substrate. The semiconductor chip has an element structure including: a silicon carbide substrate that has a hexagonal crystal structure; a gate electrode that is disposed on a part above a first surface corresponding to a (0001) plane or a (000-1) plane of the silicon carbide substrate; an insulating film that is interposed between the silicon carbide substrate and the gate electrode; and a source and a drain that are disposed with respect to the silicon carbide substrate and the gate electrode such that at least a part of a channel through which a carrier moves extends in a &#x3c;1-100&#x3e; direction of crystal orientation of the silicon carbide substrate. The mounting substrate is fixed with the semiconductor chip such that compressive stress in a &#x3c;11-20&#x3e; direction of crystal orientation of the silicon carbide substrate is applied to the semiconductor chip at least in operation.

Semiconductor device and method of manufacturing the same

An image processing apparatus according to an embodiment includes a processing circuitry. The processing circuitry is configured to obtain images in a time series including images of a blood vessel of a subject and correlation information indicating a correlational relationship between physical indices of the blood vessel and function indices of the blood vessel related to vascular hemodynamics, calculate blood vessel morphology indices in a time series indicating morphology of the blood vessel of the subject, on a basis of the images in the time series, and identify a function index of the blood vessel of the subject, by using a physical index of the blood vessel of the subject obtained from the blood vessel morphology indices, on a basis of the correlation information.

Image processing apparatus, image processing method, and storage medium

Growing community of inventors

Kanagawa, Japan

Akihiro Goryu