Matsushita Electric Industrial Co., Ltd.

Akihira Shinohara

Takashi Uehara

Takashi Nakabayashi

Mizuki Segawa

Yoshiaki Kato

Hiroshi Masuda

Atsushi Hori

Hiroaki Nakaoka

Mitsuo Yasuhira

Ichiro Matsuo

Kiyoyuki Morita

Keiichi Kagawa

Akio Miyajima

Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Manufacturing method of CMOS transistor

Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment. P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.

Manufacturing method of CMOS transistor with no reduction of

A semiconductor apparatus with MOS transistors for transmitting electrons from an n type source layer to an n type drain layer through a first channel region in an n-channel MOS transistor and transmitting holes from a p type source layer to a p type drain layer through a second channel region in a p-channel MOS transistor consists of a field oxide layer for separating the n-channel MOS transistor from the p-channel MOS transistor, an n type gate electrode mounted on a first gate oxide film arranged on the first channel region, a p type gate electrode mounted on a second gate oxide film arranged on the second channel region and positioned far away from the n type gate electrode to prevent impurities implanted into one of tile gate electrodes from diffusing into the other gate electrode, and a gate metal wiring connecting the gate electrodes through a gate contact hole to miniaturize the transistors.

Semiconductor apparatus having an n-channel MOS transistor and a

Manufacturing method of CMOS transistor including heat treatments of

Manufacturing method of CMOS transistor in which heat treatment at

An ion implantation stopper is formed on a gate electrode extending on a substrate. When ions are implanted into the substrate to form an LDD layer or source and drain regions in the substrate, the stopper functions to prevent the gate electrode from being exposed to ion implantation. The prevention of the exposure of the gate electrode to the ion implantation ensures the prevention of channeling in the gate electrode. The invention includes forming a first protective film on the gate of an NMOS, implanting to form LDD region for the NMOS, implanting to form source and drain regions of a PMOS, forming a second protective film on the gate of the NMOS, implanting to form source and drain regions of the NMOS, the first and second protective films prevent the gate electrode of the NMOS from being exposed to ion implantation during the respective implanting steps so that channeling is prevented from occurring in the gate electrode of the NMOS.

Method of fabricating a CMOS semiconductor devices

An ion implantation stopper is formed on a gate electrode extending on a substrate. When ions are implanted into the substrate to form an LDD layer or source and drain regions in the substrate, the stopper functions to prevent the gate electrode from being exposed to ion implantation. The prevention of the exposure of the gate electrode to the ion implantation ensures the prevention of channeling in the gate electrode.

Method of fabricating a CMOS semiconductor device

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Osaka, Japan

Akihira Shinohara