Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Matsushita Electronics Corporation

Akihiko Tsuzumitani

Yoshihiro Mori

Yasutoshi Okuno

Hisashi Ogawa

Kenshi Kanegae

Atsushi Ikeda

Toshihiko Nagai

In order that a top surface of a gate electrode does not have sharp portions, ends of the top surface of the gate electrode are rounded before refractory metal is deposited for silicidation. This reduces intensive application of film stresses which are generated in heat treatment, enabling formation of a silicide layer with a uniform, sufficient thickness.

Semiconductor device and manufacturing method thereof

A semiconductor device of a dual-gate structure including a P-channel type field-effect transistor formed at a first region of a substrate and an N-channel type field-effect transistor formed at a second region of the substrate, includes a gate electrode including a polycrystalline silicon film continuously formed on the substrate to cover the first and second regions and a metal silicide film formed on the polycrystalline silicon film. The polycrystalline silicon film has a P-type part located on the first region and an N-type part coming into contact with the P-type part and located on the second region, and the P-type part is further doped with a heavier element than a P-type impurity that determines a conductivity type of the P-type part.

Semiconductor device and method for fabricating the same

Semiconductor device and manufacturing method thereof with rounded gate including a silicide on the top and at the corners

A measurement substratein which a silicon oxide film, a polysilicon layerand a titanium silicide layerare formed over a silicon substratein this order is prepared. The measurement substrateis irradiated with X-rays so that the proportions of three types of silicides with different compositions in the titanium silicide layerare measured based on the intensity of hard X-rays emitted from oxygen in the silicon oxide filmand the intensity of hard X-rays emitted from titanium in the titanium silicide layer

Method for measuring silicide proportion, method for measuring annealing temperature, method for fabricating semiconductor device and x-ray photo receiver

In a memory cell of a DRAM, that is, a semiconductor memory, a bit line connected to a bit line plug and a local interconnect are provided on a first interlayer insulating film. A connection conductor film of TiAlN is provided on the top and side faces of an upper barrier metal and side faces of a Pt film and a BST film. No contact is formed above the Pt film used for forming an upper electrode, and the upper electrode is connected to an upper interconnect (namely, a Cu interconnect) through the connection conductor film, a dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, the characteristic degradation of a capacitor insulating film can be prevented.

Semiconductor memory and method for fabricating the same

A semiconductor device has a capacitance insulating film having a perovskite structure represented by the general formula ABO(where each of A and B is a metal element) and first and second electrodes opposed to each other with the capacitance insulating film interposed therebetween. The capacitance insulating film is formed such that the composition of the metal element A or B is higher in the region thereof adjacent the first electrode than in the other region thereof.

Method for fabricating a semiconductor device including a capacitance insulating film having a perovskite structure

A memory cell in a DRAM, which is a semiconductor memory device, is provided with a bit line connected to a bit line plug and a local interconnect , over a first interlevel insulating film . A conductor sidewall of TiAlN is formed on side faces of hard mask , upper barrier metal , Pt film and BST film . No contact hole is provided on the Pt film constituting an upper electrode . The upper electrode is connected to an upper interconnect (a Cu interconnect ) via the conductor sidewall , dummy lower electrode , dummy cell plug and local interconnect . The Pt film is not exposed to a reducing atmosphere, and therefore deterioration in characteristics of the capacitive insulating film can be prevented.

Semiconductor memory device and method for fabricating the same

The invention provides a method for fabricating a semiconductor device including a concaved capacitor device having a lower electrode, a capacitor dielectric film of a perovskite type high dielectric constant or ferroelectric material formed on the lower electrode and an upper electrode formed on the capacitor dielectric film. In this method, a step of forming a conducting film to be formed into the lower electrode includes sub-steps of forming a lower conducting film by sputtering on walls and a bottom of a recess formed in an insulating film on a substrate; and forming an upper conducting film on the lower conducting film by CVD.

Method for fabricating semiconductor device

In a DRAM memory cell that is a semiconductor memory device, a bit line connected to a bit line plug and local interconnect are provided on a first interlayer insulating film. A contact is not provided on a Pt film constituting an upper electrode, and a dummy lower electrode is in direct contact with a dummy barrier metal. That is, the upper electrode is connected to upper layer interconnect (Cu interconnect) by the dummy lower electrode, a dummy cell plug and the local interconnect. Since the Pt film is not exposed to a reducing atmosphere, deterioration of characteristics of a capacitive insulating film can be prevented.

DRAM memory cell with dummy lower electrode for connection between upper electrode and upper layer interconnect

After a metal layer is formed on a dielectric film, the metal layer is subjected to an oxidation process using a liquid having oxidizing power, thereby forming an adhesion layer. Then, an electrode or wiring is formed on the adhesion layer.

Method for manufacturing semiconductor device

A semiconductor device of the present invention includes an electrode, which is formed over a substrate and contains ruthenium. Crystal grains of ruthenium in the electrode have stepped surfaces.

Growing community of inventors

Osaka, Japan

Akihiko Tsuzumitani