Yamaha Corporation

Akihiko Toda

Masao Noro

Toshio Maejima

Tatsuya Kishii

Kunito Takahashi

A plug connector includes: a jack portion into which a pin of a microphone-equipped headphone plug in which a speaker contact portion connected to a speaker of a headphone, a ground contact portion connected to a ground wire of the headphone, and a microphone contact portion connected to a microphone of the headphone are sequentially formed in an axial direction, the jack portion having a first contact which is in contact with the speaker contact portion, a second contact which is in contact with the ground contact portion, and a third contact which is in contact with the microphone contact portion; a bias circuit configured to supply a bias voltage to the third contact through a resistor; and a control circuit configured to detect that the pin is extracted from the jack portion, based on a change of a potential of the third contact.

Plug connector

A test signal supplying device includes a first external terminal, a second external terminal being applied with a predetermined electric potential, an internal load, a first terminal that is connected to the first external terminal through the internal load, a second terminal that is connected to the first external terminal without passing through the internal load, a test signal generating section that generates a test signal and supplies the test signal to the second terminal, a detecting section that detects an amplitude of the test signal, and a controlling section that measures an impedance of an external load connected to the first and second external terminals based on the detected amplitude of the test signal.

Test signal supplying device and semiconductor integrated circuit

A D/A converter formed on a semiconductor substrate includes a plurality of resistance strings which are provided between a low voltage terminal and a high voltage terminal, each of the resistance strings including a plurality of resistances connected in series. The resistance strings to be connected at odd-numbered positions are arranged on the substrate in order of increasing in a direction from a near side of the terminal to which the low voltage is applied to the far side thereof, and the resistance strings to be connected at even-numbered positions are arranged on the substrate in order of increasing in a direction from the far side of the terminal to the near side. A voltage at a junction point of the resistances constituting the resistance string is selectively output in accordance with input data to be converted.

D/A converter

A signal level shift circuit is provided for different circuit systems operating based on different supply voltages (VDDL, VDDH), wherein a supply voltage detection circuit detects a reduction of a first supply voltage (VDDL) regarding an input signal (IN). A level shift circuit comprises a load circuit portion consisting of PMOS transistors and a drive circuit portion consisting of NMOS transistors, all of which are connected together to form current paths. A switch circuit arranged for the current paths opens when a reduction is detected in the first supply voltage so that both the NMOS transistors are turned on. Thus, it is possible to effectively avoid occurrence of through currents flowing in the level shift circuit. The level shift circuit is followed by a flip-flop, which provides an output signal (OUT) in conformity with a second supply voltage (VDDH).

Circuit for shifting an input signal level including compensation for supply voltage variation

There is provided a D/A converter that is free from a variation in the voltage width of 1 LSB between more significant bits and less significant bits of data for conversion due to variations in characteristics of resistors, transistors, etc. to thereby ensure a higher conversion accuracy than the conventional D/A converter. The eight more significant bits of 12-bit data for conversion are applied to a decoder , while the four less significant bits of the same are applied to a current addition circuit . The decoder selects one of FET's F to F based on the eight more significant bits to cause one of voltages divided by a series circuit formed by resistors r to r to be applied to an operational amplifier . On the other hand, switches to of the current addition circuit are switched, respectively, by the four less significant bits to turn respective FET's to on and off. As a result, currents flowing through turned-on ones of the FET's to are synthesized to flow through the resistor ra so that a voltage is generated across the resistor ra. The operational amplifier synthesizes the two voltages and then outputs the synthesized voltage. An FET and each of the FET's to form a current mirror circuit, whereby the influence of variations in characteristics of the resistors, etc. is eliminated.

Digital-to-analog converter

Level shift circuit

A digital-to-analog-converter is provided which allows a use to set the reference voltage as desired and therefore has improved flexibility. A more significant bit data conversion section converts more significant bit data of digital data into a more significant analog signal corresponding to the more significant bit data by using a reference voltage inputted from outside. A less significant bit data conversion section converts less significant bit data of the digital data into a less significant analog signal corresponding to the less significant bit data. A controller controls the less significant bit data conversion section in such a manner as to output the less significant analog signal according to the reference voltage. An adder adds the more significant analog signal and the less significant analog signal, thereby outputting an analog signal corresponding to the digital data.

Adjustable digital-to-analog converter

An information-discriminating circuit has a biasing device that superposes bias voltage on an input signal, and a comparator that discriminates information by comparing an output signal from the biasing device with a threshold value. The difference between the bias voltage and the threshold value is continuously adjusted such that a noise margin is varied according to the amplitude of the input signal.

Information-discriminating circuit

A digital-to-analog (D/A) converter provides superior linearity and reduces glitches by setting optimum dimensions for MOS transistors. The D/A converter is configured from a R-2R ladder circuit and a switching circuit. The R-2R ladder circuit consists of series resistors (R) and shunt resistors (2R), which are connected together at respective nodes corresponding to the bit stages. The switching circuit is configured from MOS transistors which are connected between reference potentials and the shunt resistors for each bit stage. The width/length (W/L) ratios of the MOS transistors are set such that the on-resistances of the transistors are sequentially increased by a factor of 2 in bit-stage descending order from the most significant bit (MSB) to the least significant bit (LSB) to maintain the linearity of the R-2R ladder circuit. Dummy gates are provided in parallel to the MOS transistors, except for the MOS transistors which correspond to the MSB, so that the same effective gate capacitance is set for each bit stage to provide uniform switching speed for each stage avoiding the occurrence of glitches.

Digital-to-analog converter utilizing MOS transistor switching circuit

A digital-to-analog converter (i.e., D/A converter) formed on a wafer comprises a decoder, transistors (e.g., field-effect transistors) and resistors. Since the wafer provides a gap between the p-well region and the n-well region, the resistance values of the resistors formed on the p-well region differ from those of the resistors formed on the n-well region. In order to cancel such difference between the resistance values, there are provided two series of resistors in parallel between a power-applying terminal and a ground terminal, wherein each of two series of resistors contain two kinds of resistors respectively formed on the p-well region and the n-well region, while a midpoint of the first series of resistors is connected with a midpoint of the second series of resistors. Due to the direct connection between two midpoints, the potential applied to these midpoints are stabilized and set at the certain fixed voltage. Thus, it is possible to obtain a desirable precision for the linear digital-to-analog conversion characteristic of the D/A converter, regardless of the difference between the resistance values of the resistors respectively formed on the p-well region and n-well region on the wafer.

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Hamamatsu, Japan

Akihiko Toda