Fujitsu Corporation

Akihiko Takada

Yukio Furukawa

Hisakazu Ohmori

Masakazu Oi

Kazuo Wani

A clock change circuit contains: a clock gate unit for receiving first and second clock signals, and detecting a timing at which both the first and second clock signals are at an inactive level to output an active timing signal indicating the timing; a delay unit for inputting a select control signal and the timing signal, and outputting a delayed select control signal the state of which is changed to the same state of the select control signal after the active timing signal is received from the clock gate unit; and a select unit for inputting the first and second clock signals, and selects one of the first and second clock signals according to the delayed select signal to output the selected clock signal.

Clock change circuit preventing spike generation by delaying selection

An undershoot eliminating circuit is provided between a pulse transformer of a pulse transmitter coupled to a transmission line and a pulse transformer driving circuit for driving the pulse transformer. The pulse transformer driving circuit has an impedance high enough to cause the pulse transmitter to be substantially isolated from the transmission line. The undershoot eliminating circuit includes a capacitor, and a switching unit. The switching unit is connected to the capacitor, and has the function of selectively connecting the capacitor to the pulse transformer driving circuit and the pulse transformer in parallel on the basis of a voltage based on a pulse wave generated by the pulse transformer driving circuit and applied across the switching unit.

Growing community of inventors

Kawasaki, Japan

Akihiko Takada