Fujitsu Corporation

Akihiko Ono

Takumi Kawai

Susumu Ozaki

A DC offset cancellation circuit that is capable of canceling a DC offset voltage occurring between a pair of differential output signals of a differential amplification circuit, while preventing a signal waveform from being distorted due to accumulation of AC components and a photo-electric pulse conversion circuit that is capable of generating an electrical pulse signal that accurately reproduces a rise timing and a fall timing of an optical pulse signal by canceling the DC offset voltage are provided. A photo-electric pulse conversion circuit is provided with a photodiode, an I-V conversion circuit, a first differential amplification circuit having a DC offset cancellation circuit, a second differential amplification circuit, a reference voltage generation circuit, and a comparison circuit. The DC offset cancellation circuit uses a changeover circuit to change a state of a low-pass filter with a hold function in synchronization with an inversion electrical pulse signal, and performs a negative feedback of a filtered signal which is generated by subjecting third differential signals to low-pass filtration or a hold filtered signal which is a filtered signal held during changeover.

DC offset cancellation circuit, differential amplification circuit with DC offset cancellation circuit, photo-electric pulse conversion circuit, pulse shaping circuit, and pulse generation circuit

A DC offset cancellation circuit that is capable of canceling a DC offset voltage occurring between a pair of differential output signals of a differential amplification circuit, while preventing a signal waveform from being distorted due to accumulation of AC components and a photo-electric pulse conversion circuit that is capable of generating an electrical pulse signal that accurately reproduces a rise timing and a fall timing of an optical pulse signal by canceling the DC offset voltage are provided. A photo-electric pulse conversion circuit is provided with a photodiode, an I&#x2013;V conversion circuit, a first differential amplification circuit having a DC offset cancellation circuit, a second differential amplification circuit, a reference voltage generation circuit, and a comparison circuit. The DC offset cancellation circuit uses a changeover circuit to change a state of a low-pass filter with a hold function in synchronization with an inversion electrical pulse signal, and performs a negative feedback of a filtered signal which is generated by subjecting third differential signals to low-pass filtration or a hold filtered signal which is a filtered signal held during changeover.

There is intended to provide a current-voltage converter capable of surely outputting a voltage output signal regardless of current intensity when converting a current input signal with wide current range into a voltage output signal. In case a current value of a current input signal Iin is small, small current regions of diodes D and D are used and current values of first bias currents IB and IB are set small. Thereby, the small current regions can be used as a region to deal with a large change rate of voltage against current and there can be obtained an effective voltage change even for a micro current. In case a current value of the current input signal Iin is large, current values of bias currents IB and IB at a constant current circuit increase to a second bias current to obtain a characteristic such that conversion voltage VM and reference voltage VP are compressed against the current input signal Iin. To obtain the compression characteristics, there is made used of a characteristic of the diodes D and D such that their terminal-to-terminal voltage against current increases monotonously forming a convex shape. Thereby, output voltage can keep compressed differential voltage in a wide current range. Accordingly, a differential amplifier circuit AMP does not need to change its dynamic range.

Current-voltage converter

A constant-current driver circuit for on-off controlling an output current at a high speed is provided. The constant-current driver circuit includes a first MOS transistor to which a reference current is provided and a second MOS transistor connected to the first MOS transistor for generating an output current having a predetermined ratio to the reference current. A switch circuit is connected to the second MOS transistor to on-off control the output current in accordance with the input signal. A bias circuit is connected to the gate of the second MOS transistor to provide a bias voltage to the gate of the second MOS transistor so that variation in the gate voltage of the second MOS transistor is suppressed.

Constant current driver circuit

A current driver circuit for writing data to a hard disk receives an input signal and generates a current for driving a load. A drive circuit supplies the load with a current. A damping circuit connected to the drive circuit restricts the current supplied to the load in accordance with a pulse signal. A damping control signal connected to the damping circuit generates the pulse signal in response to the input signal and provides the pulse signal to the damping circuit.

Current driver circuit with a damping circuit

A driver circuit is disclosed, capable of performing a stable damping operation with a simple circuit configuration without the need of external regulation and without being influenced by specification changes and variations in load and driver current IO, wherein, in a damping circuit, a diode-connected transistor and a damping current limiting resistor are connected between an NPN transistor with the base thereof controlled by a damping circuit control signal and an output terminal, likewise, in a damping control circuit, the resistance ratio of ON resistance of a PMOS transistor and a resistor relative to ON resistance of a PMOS transistor and a load resistor is set to m times, and a current ratio of a first bias current relative to a driver constant current circuit is set to (1/N) times, and a relation between a damping control signal and a low potential-side voltage at the output terminal is set to &Dgr;Vdo&equals;((m/N)&minus;1)&times;RDRV&times;IO<Vbe 7&plus;Vbe 8, thereby preventing a damping malfunction.

Driver circuit

A noise eliminating circuit eliminates thermal asperity noise in a reproduction signal generated by a magnetic read head in a disk drive. The noise eliminating circuit includes a differential amplifier that receives the reproduction signal and a feedback signal and generates an amplified signal. A detection circuit connected to the differential amplifier detects noise in the amplified signal and generates a control signal. The control signal is activated when the noise is detected. A feedback circuit connected to the differential amplifier and the detection circuit cuts off the amplified signal with a first cutoff frequency when the control signal is not active and cuts off the amplified signal with a second cutoff frequency when the control signal is active.

Noise eliminating circuit

An AGC circuit varies a bandwidth of an input unit and accuracy of linearity of the AGC output. A first input unit converts a first input current into a first voltage. A second input unit, identical to the first input unit, converts a second input current into a second voltage. A variable constant current source generates first and second constant currents. The first constant current flows from the first input unit to the variable constant current source. The second constant current flows from the second input unit to the variable constant current source. The first and second constant currents are varied by a control signal supplied by an external signal source so that the bandwidths of the first and second input units are varied. The AGC output of the AGC circuit is calculated based on the first voltage and the second voltage.

Growing community of inventors

Kasugai, Japan

Akihiko Ono