Sony Corporation

Siemens Aktiengesellschaft

Akihiko Ochiai

Hisayoshi Yamoto

Masahiro Tanaka

Hiroshi Sato

Takeshi Matsushita

Makoto Hashimoto

Shun Mitarai

Machio Yamagishi

Yasuyuki Ito

Muneharu Shimanoe

Katsuaki Asano

A trench is formed by forming a photoresist film on a second interlevel insulator and performing isoprotonic etching using the photoresist film as a mask. A lower electrode layer made of platinum (Pt), a dielectric film made of a dielectric material and an upper electrode layer made of platinum (Pt) are formed in this order by, for example, a CVD method respectively. Further, the lower electrode layer and the upper electrode layer are selectively removed by a CMP method except for the trench with the second interlevel insulator as an end point detection layer, flattening the surface at the same time. Accordingly, a capacitor having a structure which has a flat surface comprised of both edges of the lower electrode layer and the dielectric film, and the upper electrode layer is formed in the trench of the second interlevel insulator respectively. Etching can be easily performed even when a stable material such as platinum is used as an electrode material, simplifying the manufacturing procedure since the lower electrode layer, the dielectric film and the upper electrode layer are processed collectively.

Method for manufacturing a dielectric trench capacitor with a stacked-layer structure

Provided is a semiconductor memory device in which defective contact, deterioration in transistor characteristics and other problems are solved with a thermally stable, conductive diffusion barrier layer against oxygen, and against constituent elements in a plug material and a lower electrode, formed at the interface between a plug and the lower electrode made of a noble metal. The semiconductor memory device comprises a dielectric capacitor of a stacked structure including a first electrode (a lower electrode), a dielectric film and a second electrode (an upper electrode) and a conductive plug connected to the lower electrode, wherein the lower electrode connected to the conductive plug includes a metal suboxide layer with conductiveness and a diffusion barrier layer blocking diffusion of oxygen, and the metal suboxide layer and the diffusion barrier layer are stacked in the order from the conductive plug side of the lower electrode.

Oxygen diffusion blocking semiconductor capacitor

A capacitor in a ferroelectric nonvolatile memory (FERAM) comprising a lower electrode formed on a semiconductor substrate; a ferroelectric thin film formed on the lower electrode; an upper electrode formed on the ferroelectric thin film; a first protective layer consisting of one or more layers formed between the semiconductor substrate and the lower electrode, and composed of a material selected from those of Group IVa transition metal, Group Va transition metal, Group IVa transition metal nitride, Group Va transition metal nitride, silicon nitride, nickel and palladium; and a second protective layer consisting of one or more layers formed on the upper electrode, and composed of a material selected from those of Group IVa transition metal, Group Va transition metal, Group IVa transition metal nitride, Group Va transition metal nitride, nickel and palladium. Since the ferroelectric capacitor is enclosed with composite films of such materials, it becomes possible to prevent diffusion of hydrogen and intrusion of water content therein to consequently avert deterioration of the characteristics.

Capacitor having ferroelectric film and multiple layers of insulating and protective films for nonvolatile memory cell

A trench is formed by forming a photoresist film on an interlevel insulator and performing isoprotonic etching using the photresist film as a mask. A lower electrode layer made of platinum (Pt), a dielectric film made of a dielectric material and an upper electrode layer made of platinum (Pt) are formed in this order by, for example, CVD method respectively. Further, the lower electrode layer and the upper electrode layer are selectively removed by CMP method except for the trench with the interlevel insulator to be an end point detection layer and the surface is flattened at the same time. Accordingly, a capacitor having a structure which has a flat surface comprised of both edges of the lower electrode layer and the dielectric film, and the upper electrode layer is formed in the trench of the interlevel insulator respectively. Etching can be easily performed even a stable material such as platinum is used as an electrode material, and so that manufacturing procedure can be simplified since the lower electrode layer, the dielectric film and the upper electrode layer are processed collectively.

Dielectric capacitor and method of manufacturing same, and dielectric memory using same

Method of manufacturing capacitor having ferroelectric film for

A capacitor structure of a semiconductor memory cell, comprises: a lower electrode formed on an insulation layer; a capacitor insulation film in form of a ferroelectric thin film formed on the lower electrode; and an upper electrode formed on the capacitor insulation layer, the lower electrode including a column-shaped projection made of a conductive material formed on the insulation layer, and a lower electrode layer covering the projection, and the ferroelectric thin film being formed on the lower electrode layer as originally stacked. A method for fabricating a capacitor structure of a semiconductor memory cell, comprises the steps of: forming a conductive material layer on an insulation layer, then patterning the conductive material layer to form a column-shaped projection of a conductive material on the insulation layer; stacking a lower electrode layer on the insulation layer including the surface of the column-shaped projection; stacking a ferroelectric thin film on the lower electrode layer as originally stacked; stacking an upper electrode layer on the ferroelectric thin film; and patterning the lower electrode layer, the ferroelectric thin film and the lower electrode layer to form a capacitor structure including a lower electrode, a capacitor insulation film in form of the ferroelectric thin film, and an upper electrode.

Semiconductor memory cell using a ferroelectric thin film and a method

A capacitor structure in a semiconductor memory cell includes a lower electrode formed on a base body, a capacitor insulation film which is a ferroelectric thin film formed on the lower electrode, and an upper electrode formed on the capacitor insulation film. The lower electrode is shaped semi-spherical. The capacitor structure has an increased area of the upper electrode in contact with the ferroelectric thin film, local concentration of an electric field in the ferroelectric thin film is unlikely to occur.

Capacitor structure of semiconductor memory cell and method for

The present invention provides a method for manufacturing a semiconductor device, including a step of forming an opening 1 such as a contact hole and a succeeding heat treatment step such as contact annealing, wherein the heat treatment is performed upon completion of filling the opening with a diffusion-preventing film 9 or the like. The method according to the present invention is free from disadvantages due to diffusion of a diffusible material during a heat treatment step performed after the step of forming an opening even if the method is applied to manufacture of a semiconductor device having a structure in which a diffusible material 2 such as a dielectric material used in a capacitor may diffuse through the opening due to heat during such a heat treatment step.

Method for manufacturing semiconductor device

A process for fabricating a semiconductor device comprising multilevel interconnection, comprising: forming a trench on the surface of a first substrate to provide an element isolating region; forming a first insulating film on the surface of the trench and the first substrate; forming a first interconnection layer on the surface of the first insulating film; forming a second insulating film on the surface of the first substrate in such a manner that the first interconnection layer is covered and the trench is filled; forming a second interconnection layer on the second insulating film; forming sequentially in this order, a third insulating film and an adhesion layer-on the surface of said second insulating film covering the second interconnection layer; bonding a second substrate on the surface of the adhesion layer; planarizing the back of the first substrate by removing the first substrate from the back side thereof and the bottom of the trench; and forming a fourth insulating film on the back of the first substrate, and forming a third interconnection layer on the fourth insulating film. The process according to the present invention enables a semiconductor device comprising a multilevel interconnection with small step height.

Process for fabricating semiconductor device having a multilevel

The invention concerns a method of forming various kinds of SOI structures and semiconductor memory devices using the forming technique. It is useful, for example, in SRAM or EEPROM devices. In EEPROM, it relates, in particular, to a method of manufacturing a non-volatile memory device in which a control gate electrode layer is laminated by way of an insulator film on a floating gate electrode layer. It includes a method of manufacturing a structure via the steps of forming an etching stopping layer on the surface of a silicon substrate, forming an epitaxially grown silicon layer on said etching stopping layer, bonding said silicon substrate formed with said silicon layer with another substrate as the insulator substrate, grinding said silicon substrate from the rear face and etching it until said etching stopping layer is exposed and removing said etching stopper layer, with or without polishing the other surface of said silicon substrate.

Method and apparatus for semiconductor memory

In a sea-of-gate structure gate array in which a plurality of logic gates are arrayed on a semiconductor chip, resistance devices or capacitive devices are formed without reducing the gate scale to form analog components to render the gate array into a hybrid gate array including the analog components. A number of MOS transistors to be formed without vacancies on the chip surface are formed in a thin silicon section on an insulating layer 15. The logic gates arrayed on the chip is of the SOI structure. Below the insulating layer 15, a lower capacitor electrode 12, a dielectric film 13, an upper capacitor electrode 14 and a resistance element are formed so as to be buried in an insulating film 11 on a supporting substrate 10 or in an insulating substrate. The capacitor and the resistance are led to the chip surface by means of a contact hole 23 provided in the insulating layer 15. A grinding stop 16 is formed in the insulating layer 15. The thin silicon section of the SOI structure is produced by grinding the substrate.

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Kanagawa, Japan

Akihiko Ochiai