Sharp Kabushiki Kaisha Corporation

Other

Akihiko Nakano

Tadao Takeda

Hiroshi Ban

Toshinori Ohmi

Eiji Yanagawa

Hideyuki Unno

Hironori Matsumoto

Fumitoshi Yasuo

Kayoko Mori

In the present semiconductor device, a chip with an LSI circuit is secured to a board (with the chip flipped) so as to be level. The LSI circuit on the chip is specified to operate normally only when the chip is level. Further, the back of the chip is processed so as to give stress to the chip. The chip has a reduced thickness of 50 &mgr;m or less (alternatively 30 &mgr;m to 50 &mgr;m). Therefore, when the chip is detached from the board, it deforms and is no longer level due to the stress, which prohibits the LSI circuit from operating normally. This way, the present semiconductor device ensures that no analysis can be conducted on the LSI circuit once the chip is detached.

Semiconductor device and method of manufacturing the same

A semiconductor device includes, on a protective film laminated on a circuit principal part, (i) a light blocking film provided so as to cover the circuit principal part, (ii) an aluminum oxide film provided so as to completely cover the light blocking film, and (iii) a light-blocking upper wiring provided on the aluminum oxide film. An attempt to exfoliate the light blocking film or the light blocking upper wiring causes the resistance-detection-use upper wiring to break or thin, thereby resulting in an increase in the resistance of the resistance-detection-use wiring. The increase in the resistance is detected by the resistance detecting circuit part, and malfunction or inoperativeness of the circuit principal part is caused in response of detection. By so doing, the circuit principal part can be protected from analysis.

Semiconductor device wherein detection of removal of wiring triggers impairing of normal operation of internal circuit

A semiconductor device in accordance with the present invention includes a semiconductor element chip pressed and secured on a distortion die-pad so that the semiconductor element chip, sealed inside a package, is held in a predetermined distorted state. The predetermined distorted state is preferably downward or upward warping. The semiconductor element chip operates normally in the distorted state, and does not operate normally when the semiconductor element chip is separated from the semiconductor device, and thereby released from the distortion and laid alone. This ensures that the semiconductor element chip is protected from circuit analysis.

A region on a surface side of a sample is irradiated with a Ga ion beam to form a first laminar portion having a thickness of 50-200 nm small enough to allow the transmission electron microscopic observation. While the sample is being heated within a transmission electron microscope, a process in which silicide is being formed is observed at the first laminar portion. Thereafter, a second laminar portion is formed in a thick region of the sample, similarly to the first laminar portion. Then, the first and second laminar portions are comparatively observed in a non-heated state with the transmission electron microscope. If observation results of the two laminar portions in the non-heated state are the same, a result of observing the first laminar portion during the heating is taken to represent a phenomenon in a bulk state. If observation results of the two laminar portions are different from each other, the result of observing the first laminar portion during the heating is taken to represent a unique phenomenon resulting from the heating of the sample in a thin film state. Thus, a transmission electron microscopic observation involving the simultaneous heat treatment is correctly carried out with a few samples.

Method for observing a reaction process by transmission electron

A reference grid for use in charged particle beam spectroscopes in analyzing an impurity contained in a target sample, which includes a grid composed of a material free of the impurity.

Impurity free reference grid for use charged partiole beam spectroscopes

An inspecting apparatus is provided by which a cross section of a semiconductor device to be inspected can be easily obtained. The inspection apparatus includes a first microscope for specifying a portion where the inspection of a cross section is to be effected, a rotary grinder for grinding the portion specified by the first microscope, a second microscope for monitoring the portion ground by the rotary grinder, and a stage for fixing the semiconductor device movable relative to the first and second microscopes and the rotary grinder.

Apparatus for inspecting a semiconductor device

An apparatus for checking a semiconductor comprising an X-Y stage for movably holding a semiconductor chip in terms of X-Y coordinates, a charged particle beam radiating device for radiating a charged particle beam on the semiconductor chip held in the X-Y stage to generate secondary electrons therefrom, a detecting device for detecting secondary electrons emitted from the semiconductor, a magnifying device for displaying an enlarged image of the semiconductor chip on the basis of data of the detected secondary electrons, a semiconductor tester for measuring electrical characteristics of the semiconductor chip to specify a defective element of circuit elements constituting the semiconductor chip on the basis of a result of the measurement, a defective portion locating device provided with table data of a layout pattern showing the relationship between the circuit elements constituting the semiconductor chip and the arrangement thereof, for obtaining on the basis of the table data position data of the defective circuit element specified by the semiconductor tester, and a control device for issuing instructions to operate the X-Y stage, charged particle beam radiating device, and magnifying device, and further to cause the charged particle beam radiating device to impress marks on the semiconductor chip for indicating a position of the defective circuit element in positions apart from the defective circuit element at predetermined spaces by the charged particle beam radiation on the basis of the position data of the defective circuit element obtained by the defective portion locating device.

Apparatus and a method for checking a semiconductor

An apparatus for checking a semiconductor comprising an X-Y stage for movably holding a semiconductor chip in terms of X-Y coordinates, a charged particle beam radiating device for radiating a charged particle beam on the semiconductor chip held in the X-Y stage to generate secondary electrons therefrom, a detecting device for detecting secondary electrons emitted from the semiconductor, a magnifying device for displaying an enlarged image of the semiconductor chip on the basis of data of the detected secondary electrons, a semiconductor tester for measuring electrical characteristics of the semiconductor chip to specify a defective element of circuit elements constituting the semiconductor chip on the basis of a result of the measurement, a defective portion locating device provided with table data of a layout pattern showing the relationship between the circuit elements consituting the semiconductor chip and the arrangement thereof, for obtaining on the basis of the table data position data of the defective circuit element specified by the semiconductor tester, and a control device for issuing instructions to operate the X-Y stage, charged particle beam radiating device, and magnifying device, and further to cause the charged particle beam radiating device to impress marks on the semiconductor chip for indicating a position of the defective circuit element in positions apart from the defective circuit element at predetermined spaces by the charged particle beam radiation on the basis of the position data of the defective circuit element obtained by the defective portion locating device.

Growing community of inventors

Nara, Japan

Akihiko Nakano