Hitachi, Ltd.

Other

Renesas Electronics Corporation

Hitachi Microcomputer System, Ltd.

Hitachi Microcomputer

Hitachi Microcomputer Systems Ltd.

Akihiko Iwaya

Masachika Masuda

Kunihiro Tsubosaki

Masahiro Ichitani

Junichi Arita

Ichiro Anjoh

Tamaki Wada

Asao Nishimura

Kunihiko Nishi

Gen Murakami

Toshio Sugano

Kazunari Suzuki

Masamichi Ishihara

Ryosuke Kimoto

Susumu Hatano

Michio Tanimoto

Yutaka Kagaya

Toshihiro Shiotsuki

Chikako Imura

Taisei Jin

Shunji Koike

Akihiro Yaguchi

Satoshi Nakamura

Mitsuaki Haneda

Atsushi Nakamura

Tomoo Matsuzawa

An object of the present invention is to improve the reliability of a semiconductor device. A semiconductor device has a first lead group comprised of a plurality of first leads, a second lead group comprised of a plurality of second leads, and a first suspension lead arranged between the first lead group and the second lead group. Further, the semiconductor device has a first tape attached to each of the first leads, the first suspension lead, and some of the second leads, and a second tape attached to each of the second leads. Further, the first tape has a lead holding part attached to each of the first leads, and a tape supporting part attached to the first suspension lead and some of the second leads and is attached to a position farther from wire connecting portion than the lead holding part.

Method of manufacturing semiconductor device

Semiconductor device

A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips are mounted on a substrate in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate Each chip has a plurality of pads which are disposed thereon into an almost linear array substantially along the center line in the direction of short side edges, which pads include addressing pads that are located on the side of central part on a specified plane of the substrate and control-use pads of control signals that are also placed on the center side of the substrate The pad array also includes input/output pads that are disposed so that these are on the peripheral side on the surface of substrate

The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.

Method of fabricating a semiconductor device

A LOC type semiconductor device comprises a semiconductor chip having a main surface in which semiconductor elements and a plurality of bonding pads are formed, and a back surface opposite the main surface; a plurality of leads each having an inner part and an outer part, and including a plurality of first leads having inner end portions extended on the main surface of the semiconductor chip and a plurality of second leads having inner end portions terminating near the semiconductor chip; bonding wires electrically connecting the bonding pads to bonding portions of the inner parts of the first and the second leads; and a sealing member sealing the semiconductor chip therein. A first bending portion is formed in the inner part of each second lead to prevent the sealing member from transformation by forming the sealing member in satisfactory resin balance between an upper portion and a lower portion of the sealing member.

A semiconductor device capable of improving the flexibility of designing electrical lead patterns for connection from chips via a substrate to external terminals by appropriately arranging the substrate structure and layout of more than one address signal as commonly shared by four separate chips is disclosed. In a surface mount type package of ball grid array (BGA), four chips are mounted on a substrate in such a manner such these are laid out in the form of an array of two rows and two columns. These four chips are such that regarding the upper side and lower side, these are in linear symmetry with respect to a center line extending in a direction along long side edges of the substrate . Each chip has a plurality of pads which are disposed thereon into an almost linear array substantially along the center line in the direction of short side edges, which pads include addressing pads that are located on the side of central part on a specified plane of the substrate , and control-use pads of control signals that are also placed on the center side of the substrate . The pad array also includes input/output pads that are disposed so that these are on the peripheral side on the surface of substrate

Surface mount-type package of ball grid array with multi-chip mounting

A method is provided for forming a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.

Method of fabricating a lead-on-chip (LOC) semiconductor device

The present invention provides a thin, inexpensive, high-performance semiconductor device provided with busbar leads, power leads and signal leads. A portion of the power lead connected to the busbar lead is depressed toward a major surface of a semiconductor chip to form a depressed portion, and the depressed portion is bonded to the major surface of the semiconductor chip by an adhesive layer. The signal lead and the busbar lead are spaced apart from the major surface of the semiconductor chip.

Lead on chip semiconductor device and method of fabricating the same

A semiconductor device in which inner leads among a plurality of leads are arranged on a circuit formation face of a semiconductor chip encapsulated by a resin encapsulating body and bonding pads formed on the circuit formation face of the chip and the inner leads are electrically connected. An adhesive is selectively applied only to the inner leads on the outermost sides arranged on both ends of the chip among the plurality of inner leads. The circuit formation face of the chip and the inner leads of the selected leads are joined with the adhesive Each of the selected leads has a step on the main face of the semiconductor chip and the leads except for the selected leads have almost straight shapes without being processed to have steps.

Resin-molded semiconductor device having a lead on chip structure

A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.

Semiconductor device with lead structure on principal surface of chip

Semiconductor device with lead structure within the planar area of the

Growing community of inventors

Tokyo, Japan

Akihiko Iwaya