Other

Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Hokkai Semiconductor Ltd.

Akihiko Hoshida

Shinji Udo

Kazuyoshi Oshima

Hiroshi Yoshioka

Michitaro Kanamitsu

Makoto Morino

Sinichi Miyatake

Manabu Tsunozaki

Kyoko Ishii

Yoshihisa Koyama

Kiichi Manita

Hidetomo Aoyagi

Koichi Nozaki

Hiyori Koyama

Kazuaki Ujiie

Kazue Kikuchi

Masahiro Sakai

A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the preset allowable value for the number of fails are provided. Accordingly, when the counted value of the counter circuit has exceeded the allowable value set to a register, the write process or erase process is not performed even when a write or erase command is inputted from an external circuit. Thereby, the required test time can be shortened for the electrically programmable and erasable nonvolatile semiconductor memory device such as a flash memory.

Nonvolatile memory device

A semiconductor integrated circuit device constituted by a plurality of sets each of which having a pair of memory mats and each memory mat having a plurality of memory cells arranged in a matrix and a sense amplifier, I/O lines for transmitting signals provided by the sense amplifiers, selecting circuitry for selecting either a condition for sending out the signals provided by the sense amplifiers on the I/O lines or a condition for not sending out the same on the I/O lines, and Y-selection lines for transmitting the selection signals. A decoder connected with selection is disposed substantially at the middle of the Y-selection lines. X- and Y-address buffers are disposed close to each other nearer to the center of the chip than X- and Y-redundant circuits. A reference voltage generating circuit is disposed nearer to the edge of the chip than an output buffer circuit. A relief selecting circuit of each memory mat is formed adjacent to a redundant line selecting circuits included in the same memory mat. At least some of wiring lines connected to each sense amplifier are formed in a wiring layer in which Y-selection lines are formed. The Y-selection lines are extended in gaps between the sense amplifiers.

Semiconductor integrated circuit device

Growing community of inventors

Akiruno, Japan

Akihiko Hoshida