Hitachi, Ltd.

Other

Hitachi Global Storage Technologies Japan, Ltd.

Hitachi Microcomputer System, Ltd.

Akihiko Hirano

Terumi Takashi

Seiichi Mita

Naoki Satoh

Akira Uragami

Ryutaro Horita

Kenichi Hase

Yoshiju Watanabe

Syoichi Miyazawa

Shinichi Kojima

Shoichi Miyazawa

Yasuhide Ouchi

Ryushi Shimokawa

Yoshiteru Ishida

Hideyuki Yamakawa

Hiroshi Kimura

Hideki Sawaguchi

Kazunori Iwabuchi

Yosuke Hori

Toshihiro Nitta

Koji Shida

Hideki Miyasaka

Tomoaki Hirai

Satoshi Minoshima

Mikio Suzuki

Eisaku Saiki

Takashi Nara

Minoru Kosuge

Takushi Nishiya

Kazuhisa Shiraishi

Kazutoshi Ashikawa

Yasuyuki Ito

Yoichi Uehara

Shoichi Miyazawa, Deceased

Masakazu Hosino

In a coding method which does not restrict a run length of '1' while data is recorded/reproduced, there are such a drawback that when an error correction is carried out, a total number of error data to be corrected is increased, and also errors of not-detectable data are increased. While data is coded, a continuous number of '1' contained in a code word is limited, and then an error correction is carried out inside a coding/decoding process operation. Thus, a recording/reproducing apparatus having a small number of decoding errors is available.

Decoding apparatus and decoding method

A maximum likelihood decoding circuit is arranged to reduce the power consumption through the effect of the Viterbi algorithm. A plurality of storing elements to located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks ( ) to (D) in a manner to correspond to the combination (state) of intra-code interferences. The outputs from the storing elements to are again applied into the inputs of the corresponding storing elements contained in the same storing element block through the path history selecting circuits to . Each of the storing element block ( ) to (D) is periodically started on the input timing of a receiving signal at each processing time point by starting points (pointers) ( ) to (D) outputted from a starting signal (pointer) generating circuit . A storing element block output circuit and storing element block output terminals ( ) to (D) are provided in each of the storing element blocks ( ) to (D) so that a path memory circuit output may be outputted through an OR circuit

Decoding circuit using path sequence including feed-back type path sequence storing blocks

In a coding method which does not restrict a run length of &ldquo;1&rdquo; while data is recorded/reproduced, there are such a drawback that when an error correction is carried out, a total number of error data to be corrected is increased, and also errors of not-detectable data are increased. While data is coded, a continuous number of &ldquo;1&rdquo; contained in a code word is limited, and then an error correction is carried out inside a coding/decoding process operation. Thus, a recording/reproducing apparatus having a small number of decoding errors is available.

Data byte errors are detected by a comparator and classified into errors for respective interleaves, and the classified errors are counted by counters in an error count block. Further, at the time one sector has been read, comparators compare the counted values for the respective interleaves with an interleave threshold to detect whether nor not there are interleaves which have a number of errors exceeding the interleave threshold, and the detected results are counted by an error count block. The frequency of retries after an ECC is predicted from the counted value on the error count block and the total number of read sectors.

Performance evaluation method, performance evaluation system, and information storage apparatus using same

A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

Signal processing circuit and information recording/reproducing apparatus using the same, and method for optimizing coefficients of equalizer circuit

Coding apparatus and coding method

A maximum likelihood decoding circuit is arranged to reduce power consumption through the effect of a Viterbi algorithm. A plurality of storing elements located vertically in a column and for storing each state survivor path information at the same time point are treated as storing element blocks in a manner to correspond to the combination (state) of intracode interferences. The outputs from the storing elements are again applied into the inputs of the corresponding storing elements contained in the same storing element block through path history selecting circuits. Each of the storing blocks is periodically started on the input timing of a receiving signal at each processing time point by starting signals (pointers) outputted from a starting signal (pointer) generated circuit. A storing element block output circuit and storing element block output terminals are provided in each of the storing element blocks so that a path memory circuit output may be outputted through an OR circuit.

Decoding circuit and information processing apparatus

A magnetic disk storage apparatus having a magnetic disk-type storage medium; a head for reading data recorded on the magnetic disk-type storage medium, a processor, a phase synchronizing circuit having a controllable response characteristic and for outputting a clock signal to handle the data read from the magnetic disk-type storage medium, and a memory for storing information to control the response characteristic of the phase synchronizing circuit previously set in accordance with an access position on the magnetic disk-type storage medium. The processor generates the access position on the magnetic disk-type storage medium and data for commanding the control of the response characteristic of the phase synchronizing circuit in accordance with the information stored in the memory, and commands the control of the response characteristic by the data for the command, at a time consistent with a time of a seek operation of the head for the access position on the magnetic disk-type storage medium or a time before the seek operation of the head. Further, the response characteristic is controlled by the command.

Magnetic disk storage apparatus

A reproduced signal processing circuit includes a variable gain amplifier to which a signal read from a medium by a reproducing head is inputted; an analog-to-digital converter for converting a signal outputted from the variable gain amplifier into a digital signal; and a variable frequency oscillator for supplying an operation clock signal to the analog-to-digital converter. A reproduced signal processing method includes the steps of operating a first control loop for controlling the variable gain amplifier; operating at least either one of a second control loop and a third control loop, the second control loop controlling the variable frequency oscillator, the third control loop controlling the variable frequency oscillator; filtering by analog filter means the read signal inputted to the variable gain amplifier; operating at least one of first, second, and third noise detecting operations, the first noise detecting operation detecting presence or absence of a noise by comparing an amplitude of the output signal from the variable gain amplifier with a predetermined threshold value, the second noise detecting operation detecting a noise during an operation period of the second control loop, the third noise detecting operation detecting a noise during an operation period of the third control loop; and changing the range of cutoff frequency of the analog filter means in accordance with a result from at least one of the first, second, and third noise detecting operations, thereby controlling at least one of the first, second, and third control loops.

Reproduced signal processing method, reproduced signal processing

A phase-locked loop included in a reproduce signal processing circuit which as a magnetic recording and reproducing device or the like. The phase-locked loop accurately detects a phase and can be operated at high speed. The phase-locked loop includes a data determining circuit for judging data at individual times from sampled data in a plurality of samples and an estimated data string generating circuit for examining the correlation between each data string and each known phase-locked data string and sequentially generating the known phase-locked data string closet to the data string. A sampling phase is detected by performing an arithmetic operation on the data string estimated by the estimated data string generating circuit and the sampled data.

Method of and apparatus for detecting phase

A magnetic disk storage apparatus provides with a phase locked loop or a phase sync circuit including a phase comparator, a charge pump, a filter and a voltage-controlled oscillator. The phase sync circuit includes a register which is connected to an information processing system and adapted to store therein the response characteristics of the phase comparator, the charge pump, the filter and the voltage-controlled oscillator as instructed from the information processing system. In this way, in accordance with the information on the response characteristics from the information processing system, the phase sync circuit is controlled thereby to assure a stable operation even in the case of the data transfer speed varying between inner and outer track such as occurs in a magnetic disk.

Magnetic disk storage apparatus with phase sync circuit having

A calculation concerning the input of a signal is removed from a branch metric calculation processing on a trellis diagram of an extended partial response class, and the calculation of branch metrics and the selection of survivor paths can be carried out by the subtraction of the survivor paths and the comparison of constants.

Digital signal decoding apparatus and a decoding method used therein

Signal processing circuit and information recording/reproducing

A phase lock loop system includes: a phase detecting circuit which operates on the basis of a signal waveform; a current output circuit for generating a current value from a phase difference detected by the phase detecting circuit; a filter which is constructed by only a resistor in a phase locked state by a synchronizing signal and by a capacitor and the resistor upon phase following state; and a voltage controlled oscillator for controlling an oscillation frequency by a voltage output of the filter. The phase lock loop system operates as a primary phase lock loop circuit in the phase locked state by the synchronizing signal and operates as a secondary phase lock loop circuit upon phase following state.

Phase lock loop system including a primary phase lock loop apparatus and

A data recording/reproducing apparatus and method therefor having a Viterbi decoder which stores operation result values of an inputted reproduced signal and the reference value when the peak value of the reproduced signal is updated, compares this value with the reproduced signal in amplitude, updates the stored value when the result satisfies the predetermined condition, detects a change in the polarity of the comparison result, controls the clock counter depending on the status of the peak value updating signal, sets 1 in the shift register at the position indicated by the counter according to the detected polarity inversion signal when the peak value is updated, and accordingly makes the updating and detecting operations independent of operations of addition and subtraction of the current reproduced signal and reference value and operations of addition and subtraction of amplitude comparison.

Data recording/reproducing apparatus having viterbi decoder and method

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Odawara, Japan

Akihiko Hirano