Sony Corporation

Akihiko Hashiguchi

Mitsuharu Ohki

Masuyoshi Kurokawa

Takao Yamazaki

Takumi Okaue

Takahiro Seki

Mitsuo Soneda

Katsunori Seno

Akira Nakagawara

Hideo Kosaka

Tetsuo Kondo

Akihiro Uda

A power supply voltage control apparatus including an input signal generation circuit of wide uses or a small-sized monitor circuit of a novel configuration, and a semiconductor circuit and a method for driving the same, having a semiconductor circuit, an input signal generation circuitable to change the phase difference i of a reference signal out&#x3c6;i and an input signal out&#x3c6;in accordance with a control signal Si when generating the two signals from a clock, a monitor circuithaving a characteristic between a power supply voltage and delay the same as that of a critical path of the semiconductor circuit, propagating the input signal out&#x3c6;, and outputting a delayed signal out&#x3c6;' to be delayed exactly by a time equivalent to a delay of the critical path (or smaller by a constant ratio), a delay detection circuitfor detecting a delay of the delayed signal out&#x3c6;&#x2032; relative to the reference signal out&#x3c6;i, and a power supply voltage control circuitfor controlling a power supply voltage Vsupplied to the semiconductor deviceand the monitor circuitbased on the detection result.

Power supply control device, semiconductor device and method of driving semiconductor device

A voltage supply circuit capable of dealing with an abrupt change of a load by controlling an amount of increase of a power source voltage to be larger than an amount of reduction, supplying a stable operating power source voltage, and realizing lower power consumption while maintaining normal operation of a semiconductor integrated circuit is provided. By providing a replica circuit , detecting a delay time of a critical path of an LSI , comparing a delay time detected by a control circuit with a predetermined reference value, performing control to raise a voltage V supplied to the LSI when the delay time is larger than the reference value as a result of the comparison and to lower the voltage V supplied to the LSI when the delay time is smaller than the reference value, and making the amount of increase at the time of raising the supplied voltage larger than the amount of reduction at the time of lowering it, when the supplied voltage V becomes smaller than the reference value, it can be quickly restored to be larger than the reference value, the time when operating error of the LSI may occur can be greatly shortened, and the operational stability of the voltage supply circuit can be improved.

Voltage supply circuit and control method of the same

A memory system and its programming method capable of reducing the programming time for each page, wherein the memory-cell array is constituted by a MONOS-type (MNOS-type) non-volatile memory or floating gate non-volatile memory in which a source-side channel, hot-electron injection that enables the memory to write therein data by each divided unit (for instance, each 64 bytes&equals;512 bits) is carried out, instead of the write operation where writing is carried out collectively by each page unit (512 bytes). Further, there is provided an emulation circuit successively storing programming data that constitute the page of a plurality of divided units and a control circuit successively reading the held divided unit data so as to write to the non-volatile memory.

Memory system and programming method thereof

A parallel processor apparatus capable of reducing the power consumption when converting serial data to parallel data and, at the same time, capable of improving an operating speed, wherein a data input register for converting serial data to parallel data is divided and data inputting means of a plurality of blocks are constituted and wherein detection circuits for detecting the time of input and the time of output of the pointer data in the data inputting means are provided and switch circuits for connecting the related data inputting means and a serial data input line only for a period from the time of input to the time of output of the pointer data detected by the detection circuit are provided.

Reduced power parallel processor apparatus

A P-type MOSFET transistor as a current source and an N-type MOSFET transistor are connected in series between a power supply and one end of a bit line that is also connected to a memory cell with the other end thereof. The gate electrode of the P-type MOSFET transistor and that of the N-type MOSFET transistor are then biased by a current capability setting circuit in such a manner that a current capability of the P-type MOSFET transistor is smaller than a current capability of a memory cell and a current capability of the N-type MOSFET transistor is larger than the current capability of the P-type MOSFET transistor.

Data determination circuit

In a level conversion circuit where the input signal is input via a flip-flop which sets its output in a high impedance state during the holding state, by adding a circuit which sets the output voltage to a predetermined potential level when the output of the flip-flop is in a high impedance state, the leakage current is reduced and a clock skew is prevented, to result in a stable operation of the level conversion circuit.

Level conversion circuit controlled by clock signal

Feedback control is performed on the potential of a bit line in accordance with a change in the potential. Meanwhile, the data which has been previously read on the bit line is temporarily latched in a D-type flip-flop. A reference voltage Vref determined by a bias circuit is offset by using an offset circuit while referring to the level of the previously read data latched in the D-type flip-flop. In this manner, a bias voltage is obtained from currently read data, and based on the bias voltage, the potential of the bit line is controlled. Thus, high-speed data determining operation is achieved, which has been previously hampered when the currently read data is reversed with respect to the data read in the previous cycle.

Data determining circuitry and data determining method

To provide a parallel processor apparatus which can perform processing with a good efficiency on signals comprised of data of different lengths. A parallel processor configured by a serial connection of a first parallel processor and a second parallel processor having n number of individual processors and (m-n) number of individual processors. For signals comprised of data of a length, serving as the unit of processing, of m or less and n or more, these parallel processors are connected and used as a single parallel processor apparatus which performs processing equivalent to that by a conventional parallel processor apparatus. For signals comprised of data of a length of n or less, these parallel processors are independently used to perform pipeline processing and thereby perform two times the amount of processing of that performed by a conventional parallel processor apparatus.

Parallel processor apparatus

Parallel processor apparatus having means for processing signals of

A memory cell circuit which enables reduction of the leak current between a bit line and a memory cell and enables realization of a high speed reading operation and writing operation, wherein a write only circuit and a read only circuit are constructed by a drive transistor and a select transistor, the drive transistor comprising an enhancement type transistor with a threshold voltage set lower than the threshold voltage of the select transistor.

Memory cell circuit independently controlled in writing and reading

A dynamic random access memory, in which a connection switch circuit is provided between the output of a sense amplifier and a data bus or between memory block, which circuit is controlled in accordance with a write/read control signal of data so as to enable the bit line signal to be read at a high speed and the layout area of the IC to be reduced.

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Kanagawa, Japan

Akihiko Hashiguchi