Nihon Musen Kabushiki Kaisha

Japan Radio Co., Ltd.

Akiharu Inoue

Kazuo Yamashita

Nobuyuki Adachi

Masahiko Egawa

Masatoyo Nishibe

A class AB push-pull drive circuit has two NPN transistors Q.sub.1, Q.sub.2 and two PNP transistors Q.sub.3, Q.sub.4, the emitters of which are connected together. A constant voltage circuit maintains voltages between the bases of transistors Q.sub.1 and Q.sub.3 and between the bases of transistors Q.sub.2 and Q.sub.4 constant. A differential input voltage is applied across the bases of the transistors Q.sub.1 and Q.sub.2. The collector currents in the transistors Q.sub.1, Q.sub.3, Q.sub.2 and Q.sub.4 increase or decrease in an exponential and differential manner. When the collector currents are in their differential relationship, they are inverted and added to provide a class AB drive current and to increase the output amplitude. The symmetry can also be improved. Since any difference between signal amplification path lengths is eliminated, a differential phase between paths is less likely to be generated in the high-frequency region. Since there is no feedback or the like for class AB drive, it is difficult for any abnormal oscillation to be produced. Since the constant voltage circuits are formed by diodes, the temperature characteristics of the transistors Q.sub.1 to Q.sub.4 can be compensated. Furthermore, the class AB push-pull drive circuit can be driven by a relatively low voltage. The bipolar transistors Q.sub.1 -Q.sub.4 may be replaced by FETs.

Class AB push-pull drive circuit, drive method therefor and class AB

A programmable frequency dividing network comprises a plurality of cascade-connected programmable frequency dividing stages each of which divides the frequency of a clock pulse by two and three based on a logic level of a preset input signal used to change a variable division ratio from one to another. In addition, there is provided a gating means for determining or detecting whether or not each of the outputs of programmable frequency dividing stages of the programmable frequency dividing network after a programmable frequency dividing stage as a second stage is brought to a predetermined pattern and an instruction signal for making a decision as to the division of the division ratio by (+1) is inputted, so as to generate the output of a logic level for causing a programmable frequency dividing stage equivalent to a first stage to divide the frequency of the clock pulse by three if it is determined to be positive in the above detection process. Then, the output of the gating means is supplied to the programmable frequency dividing stage corresponding to the first stage in the programmable frequency dividing network so as to select either one of division ratios of n and (n+ 1) with respect to a programmable frequency dividing apparatus comprising the above network and the gating means.

Programmable frequency dividing apparatus

A slip phase control phase-locked loop includes a voltage-controlled oscillator for generating a frequency signal, and a binary programmable frequency divider for producing a frequency-divided signal in response to the frequency signal supplied thereto, the binary programmable frequency divider including a 2-scale-factor prescaler, a swallow counter, and a main counter. The phase of the frequency-divided signal is compared with the phase of a reference frequency signal. A phase-compared signal is integrated and the integrated signal is applied to the voltage-controlled oscillator. A D/A converter swallow counter and a D/A converter counter are operable with the binary programmable frequency divider for D/A-converting a signal derived from the frequency signal into a pulse-width-modulated signal corresponding to the phase-compared signal at a present count ranging from 0 to 2.sup.M -1, where M is a positive integer.

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Mitaka, Japan

Akiharu Inoue