Cadence Design Systems, Inc.

Aki Fujimura

Louis K Scheffer

Li J Song

Robert C Pack

Narain D Arora

Kenji Yoshida

Yoshikuni Abe

The present invention relates to techniques for measuring integrated circuit interconnect process parameters. The techniques are applicable to any non-ideally shaped interconnects made from any type of conductive materials. Test structures are fabricated within an integrated circuit. Non-destructive electrical measurements are taken from the test structures to determine coupling capacitances associated with the test structures. A field solver uses the initial process parameters to determine design coupling capacitances. An optimizer then uses the measured coupling capacitances and the design coupling capacitances to determine the interconnect process parameters.

Measurement of integrated circuit interconnect process parameters

To increase the writing speed of masks, context information can be used to distinguish the attributes of portions of the mask that are critical from attributes, and portions, that are less critical. By using this information, which may be derived from the design context of the features, the mask can be written at a higher speed without sacrificing the accuracy of the important attributes or features.

Method for creating patterns for producing integrated circuits

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Saratoga, CA, United States of America

Aki Fujimura