Globalfoundries Inc.

Marvell Asia Pte., Ltd.

Akhilesh Patil

Igor Arsovski

Eric D Hunt-Schroeder

Robert Maurice Houle

Michael Thomas Fragano

Van D Butler

The present disclosure relates to in-memory computing using a static random access memory (SRAM). In particular, the present disclosure relates to a structure including a memory configured to store a first word and a second word, the memory further includes a configurable data path circuit, and the configured data path circuit is configured to perform an arithmetic logical operation based on the first word and the second word in parallel.

In-memory computing using a static random-access memory (SRAM)

The present disclosure relates to a structure including a read controller configured to receive a burst enable signal and a word line pulse signal, identify consecutive read operations from storage cells accessed via a word line, precharge bit lines once during consecutive, sequential reads, and hold the word line active through N&#x2212;of the consecutive read operations, and N is an integer number of the consecutive read operations.

High-density high-bandwidth static random access memory (SRAM) with phase shifted sequential read

The present disclosure relates to a structure including a sequential mode read controller which is configured to receive a sequential read enable burst signal and a starting word line address, identify consecutive read operations from an array of storage cells accessed via a plurality of word lines, precharge a plurality of bit lines of the storage cells no more than once during the consecutive read operations, and hold a word line of the word lines active throughout the consecutive read operations. The sequential read enable burst signal and a starting word line address are decoded to select a row address and activate the corresponding word line from a plurality of word lines in the array.

Sequential read mode static random access memory (SRAM)

The present disclosure relates to a pre-charge circuit including a first inverter which receives an early pre-charge signal and outputs an inverted early pre-charge signal, a first gate which receives a late pre-charge signal and a match line output signal and outputs an AND output signal, and a second gate which receives the inverted early pre-charge signal and the AND output signal and outputs an effective pre-charge signal.

Growing community of inventors

South Burlington, VT, United States of America

Akhilesh Patil