Intel Corporation

Akhilesh P Rallabandi

Feras Eid

Joe F Walczyk

Weihua Tang

Carin Ruiz

Marco Aurelio Cartas Ayala

James G Hermerding, Ii

John C Johnson

Chee Lim Nge

Jianfang Olena Zhu

Bo Qiu

Srikanth Potluri

Deepak Samuel Kirubakaran

Mark J Gallina

Nader N Abazarnia

Christopher Wade Ackerman

Jerrod Peterson

Columbia Mishra

Morten S Jensen

Ruander Cardenas

Christopher Roy Schroeder

Mark Macdonald

James R Hastings

Renji Thomas

Sankarananda Basak

David Won-jun Song

Gaurav Patankar

Arijit Chattopadhyay

James Hermerding Ii

Carin Lundquist Ruiz

Disclosed herein are devices, methods, and systems for cooling an electronic component. The cooling device includes a liquid cooling loop with a heat exchanger, wherein the liquid cooling loop thermally conductively connects to the electronic component. The cooling device also includes a vapor compression cooling loop with a compressor and an expansion nozzle. The cooling device also includes an intermediate heat exchanger between the liquid cooling loop and the vapor compression cooling loop for exchanging heat between the liquid cooling loop and the vapor compression cooling loop. The cooling device also includes a controller configured to selectively activate the vapor compression cooling loop based on a power consumption of the electronic component.

Vapor compression assisted liquid cooling system for electronic components

An integrated circuit (IC) die structure comprises a substrate material comprising silicon. Integrated circuitry is over a first side of the substrate material. A composite layer is in direct contact with a second side of the substrate material. The second side is opposite the first side. The composite layer comprises a first constituent material associated with a first linear coefficient of thermal expansion (CTE), and a first thermal conductivity exceeding that of the substrate. The composite layer also comprises a second constituent material associated with a second CTE that is lower than the first, and a second thermal conductivity exceeding that of the substrate.

Hybrid backside thermal structures for enhanced ic packages

Heterogeneous heat pipe solutions provide both low thermal resistance and a high Q. Some heterogeneous heat pipe solutions comprise multiple homogenous heat pipes operating in parallel, with each homogeneous heat pipe having its thermal performance tailored to handle a processor operating in a particular power mode. Other heterogeneous heat pipe solutions comprise one or more heterogeneous heat pipes, each heterogeneous heat pipe having more than wick, each wick having a different set of wick characteristics (wick material, wick thickness, etc.). Heterogeneous heat pipes can provide a thermal management solution for processors over their full operating power range.

Interleaved heterogeneous heat pipes with different Q

Methods, apparatus, and systems to dynamically schedule a workload to among compute blocks based on temperature are disclosed. An apparatus to schedule a workload to at least one of a plurality of compute blocks based on temperature includes a prediction engine to determine (i) a first predicted temperature of a first compute block of the plurality of compute blocks and (ii) a second predicted temperature of a second compute block of the plurality of compute blocks. The apparatus also includes a selector to select between the first compute block and the second compute block for assignment of the workload. The selection is based on which of the first and second predicted temperatures is lower. The apparatus further includes a workload scheduler to assign the workload to the selected one of the first or second compute blocks.

Methods, apparatus, and systems to dynamically schedule workloads among compute resources based on temperature

Hybrid backside thermal structures for enhanced IC packages

Particular embodiments described herein provide for an electronic device that can be configured to enable a segmented heatsink. The electronic device can include a printed circuit board, a substrate, where the substrate is over the printed circuit board, at least two heat sources over the substrate, and a segmented heatsink secured to the printed circuit board, where the segmented heatsink has at least two independent heatsink segments, where each heatsink segment corresponds to at least one heat source and is configured to draw heat from the corresponding heat source. In an example, the heat sources are at a different height.

Segmented heatsink

Techniques for thermal management of a device under test are discussed. In an example, an apparatus may include a pedestal having a device-specific surface configured to exchange heat with the integrated circuit while the device-specific surface is in contact with a surface of the integrated circuit or separated from the surface of the integrated circuit by a layer of thermally conductive material, and a heat generating element configured to heat the device-specific surface. In certain examples, the pedestal may include a plurality of channels configured to couple to a manifold and to route thermal material from the manifold through an interior of the pedestal for maintaining temperature control of the surface of an integrated circuit under test.

System for thermal management of device under test (DUT)

Growing community of inventors

Portland, OR, United States of America

Akhilesh P Rallabandi