Stmicroelectronics International N.v.

Stmicroelectronics Pvt. Ltd.

Cadence Design Systems, Inc.

Nxp B.v.

Nxp Usa, Inc.

Akhil Garg

Prashant Dubey

Sahil Jain

Swapnil Bahl

Sravan Kumar Bhaskarani

Vivek Chickermane

Dale Meehl

Rishabh Kaistha

Amit Kashyap

Kunal Singh Sengar

A single event upset (SEU) hardened flip-flop comprises a master latch and a plurality of slave latches, where an output of the master latch is coupled to a respective input of the slave latches. A Muller element which has an input which is coupled to a respective output of the slave latches and an output which is coupled to a bus keeper. The bus keeper maintains a logic level output in presence of the SEU.

Single event upset hardened flip-flop and methods of operation

A system-on-chip (SoC) is disclosed. The SoC includes a set of input channels, a first partition including a set of output wrapper chains, a set of output channels, a second partition including a set of input wrapper chains, and an inter-partition circuit coupled between the first and second partitions. During an external test mode, the set of input channels receives input test data. The set of output wrapper chains receives and stores intermediate data that is generated based on the input test data. The inter-partition circuit receives the intermediate data from the set of output wrapper chains and generates test response data based on the intermediate data. The set of input wrapper chains receives the test response data, and provides the test response data to be captured as output test data at the set of output channels to test the inter-partition circuit.

Scan wrapper architecture for system-on-chip

A test circuit includes a plurality of codec logic elements arranged in a plurality of annular rings on an integrated circuit, each codec logic element configured to provide test bits to one or more respective scan chain and receive test result bits from the one or more respective scan chain. The test circuit further includes a decompressor logic arranged along at least one annular ring of the plurality of annular rings on the integrated circuit, the decompressor logic configured to provide test bits to at least one codec logic element in each annular ring. The test circuit also includes a compressor logic arranged transversely with respect to the plurality of annular rings on the integrated circuit, the compressor logic configured to receive test result bits from at least one of the plurality of codec logic elements.

Test circuitry with annularly arranged compressor and decompressor elements

Embodiments relate to providing security of scan mode access and data in an integrated circuit. In embodiments, one or both of two layers of security are provided. A first layer includes requiring a complex initialization sequence to be performed in order to access scan mode. A second layer includes scrambling the scan data before it is output from the circuit under test, which prevents unauthorized persons from extracting useful information from the output scan data. Further embodiments relate to methodologies for utilizing these protection layers after manufacture of the integrated circuit and incorporating these protection layers in an integrated circuit design flow.

Securing access to integrated circuit scan mode and data

A system for testing multi-clock domains in an integrated circuit (IC) includes a plurality of clock sources coupled to a plurality of clock controllers. Each of the clock sources generates a fast clock associated with one of the multi-clock domains. Each of the clock controllers is configured to provide capture pulses to test one clock domain. The capture pulses provided to a clock domain are at a frequency of a fast clock associated with the clock domain. The clock controllers operate sequentially to provide the capture pulses to test the clock domains.

Testing of multi-clock domains

A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same are disclosed. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self-testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self-test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

Locally synchronous shared BIST architecture for testing embedded memories with asynchronous interfaces

The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array.

System and method for efficient detection and restoration of data storage array defects

A system and method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories. The present disclosure further provides a programmable shared built in self testing (BIST) architecture utilizing globally asynchronous and locally synchronous (GALS) methodology for testing multiple memories. The built in self test (BIST) architecture includes a programmable master controller, multiple memory wrappers, and an interface. The interface can be a globally asynchronous and locally synchronous (GALS) interface.

A method of sharing testing components for multiple embedded memories and the memory system incorporating the same. The memory system includes multiple test controllers, multiple interface devices, a main controller, and a serial interface. The main controller is used for initializing testing of each of the dissimilar memory groups using a serial interface and local test controllers. The memory system results in reduced routing congestion and faster testing of plurality of dissimilar memories.

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Greater Noida, India

Akhil Garg