International Business Machines Corporation

Akella V Satya

James Hsi-Tang Lee

David J Perlman

Ashwin K Ghatalia

Donald R Thomas

George L Bond

Charles B Humphreys

Helen Janet Kelly

Leon Ray Bentson

Michael D Cowan

Barry N Casowitz

Tessema Kebede

Bernd K Lessmann

According to the preferred embodiment, a defect monitor is provided that facilitates the location and characterization of defects in a semiconductor device. The defect monitors are designed to facilitate automated scanning electron microscope in voltage contrast mode (SEM-VC) inspection. The defect monitors include a plurality of flags used to quickly locate defects. The SEM-VC magnification can then be increased to further isolate and characterize the defects as necessary. Thus, the preferred embodiment facilitates the use of SEM-VC scanning procedures to automatically detect and locate faults at low magnification, and then characterize the faults a higher magnification, resulting in a much higher throughput.

Defect monitor and method for automated contactless inline wafer

A memory system is provided with a simple flexible control arrangement for assigning locations in an alternate memory as replacements for previously identified defective fault areas in main memory. The assignment of the replacement locations in the alternate memory is made on a selective basis taking into consideration the defect status of other failure independent bit positions of a data word and the power of the ECC code which is used in connection with the memory system. A relatively small writable index, which is addressed by a subset of the main memory address signals, provides a partial address and control fields to the alternate memory in accordance with control data transferred from the host system. Control data is developed by the host system each time it is powered on and is based on identifying each defective location in main memory through a diagnostic routine and analyzing the defect distribution in a way to provide control signals which minimize the number of replacements that are assigned and maximize the number of data words that can be transferred from the memory system to the host system before an uncorrectable error is encountered by the ECC system.

Memory system with selective assignment of spare locations

Disclosed is a test site for an integrated circuit chip including a CCD register. Two serial CCD registers are spaced from each other at incrementally variable intervals. The first register receives a serial bit stream having a first binary value while the second serial register receives a bit stream having a second binary value. Data is transferred in parallel from the second register to determine the point at which the spacing between the two registers is sufficiently close to permit undesirable cross-talk.

Test site for a charged coupled device (CCD) array

A complex test structure for integrated, semiconductor circuits in which the impurity regions of the test device are elongated, preferably in serpentine fashion. The elongated impurity regions emulate corresponding regions in regular integrated circuit devices. Additional regions are provided, each in elongated form, which, when impressed with appropriate voltages or currents, provide indications of defect levels and product yield in the regular devices. Advantageously, the serpentine test structure is fabricated on the same wafer and with the same process steps as the regular integrated circuit chips. In one embodiment, a plurality of such monitors are provided adjacent each other in the same test site. Regions in one monitor are selectively connected to regions in another monitor and to external contact pads by contact stations disposed between each monitor.

Integrated circuit test structure

An electrical defect density monitor for semiconductor device fabrication utilizing a silicide of a formed transitional metal (such as platinum silicide) on a surface of a silicon substrate as a resistor in parallel with the resistance of the underlying substrate, including diffused regions, to improve measurement sensitivity of high sheet resistivity areas. The measurement can be employed for measuring the integrity of diffused regions and/or of dielectric coatings.

Monitor for semiconductor diffusion operations

A semiconductor defect monitoring structure employs a series of electrically testable serpentine stripe patterns having different widths and spacing in order to determine the distribution of the density of defects by size. Metal stripe patterns are superposed and rotated 90.degree. with respect to diffusion stripe patterns in a semiconductor wafer. A set of four field effect transistor devices are connected to each stripe pattern in such a way that tests may be made for all defects without interference between adjacent patterns. The defect monitoring structure helps to determine defects such as opens in diffusion and metallization, shorts in metallization, shorts in diffusion, pinholes in a thin oxide, and pinholes in a thick oxide.

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Wappingers Falls, NY, United States of America

Akella V Satya