Cadence Design Systems, Inc.

Akash Sharma

Quang Nguyen

Zhanhe Shi

Duc The Dang

Vasant Ramabadran

David Abada

Raju Joshi

A method for providing, based on an emulation schedule, a reset message to multiple circuits is provided. The reset message associates a reset signal with a selected clock cycle for each circuit, in the emulation schedule. The method includes determining a mask for each of the circuits based on the emulation schedule, providing a clock signal to the circuits, the clock signal comprising the selected clock cycle for each circuit, and tuning the reset signal relative to the clock signal based on a center of the selected clock cycle for each circuit. The method also includes providing the reset signal to the circuits and asserting the reset signal in the circuits based on the mask. A system and a non-transitory, machine-readable medium storing instructions to perform the above method are also provided.

Synchronized reset for a circuit emulator

An apparatus and method for implementing synchronous triggers for waveform capture in a multiple FPGA system is described. The apparatus includes trigger net circuitry that has one or more trigger nets and an output. Furthermore, a plurality of programmable logic devices are provided with each logic device including logic circuitry that is programmable to correspond to a circuit design, a logic analyzer circuit that includes logic connections coupled to the logic circuitry to monitor operating signals of the circuit design, and a register with a data input that is coupled to the output of the trigger net circuitry and an output that is coupled to a control input of the logic analyzer circuit. The trigger net circuitry outputs a control signal that is applied to all registers such that each logic analyzer circuit is controlled to concurrently capture data waveforms.

Implementing synchronous triggers for waveform capture in an FPGA prototyping system

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San Jose, CA, United States of America

Akash Sharma