Synopsys, Inc.

Cisco Technology, Inc.

Teja Technologies, Inc.

Arc International I.p., Inc.

Akash Renukadas Deshpande

Roberto Attias

Vineet Gupta

Navendu Sinha

Shobhit Sonakiya

William Charles Jordan

Bryon Irwin Moyer

Stephen John Joseph Fricke

Pradosh Mohapatra

Michael E Lipman

Rajagopalan M Ammanur

Marco Zandonadi

Samir D Thoria

John H W Bettink

Kannan Devarajan

Prabhakara R Yellai

Anthony Joseph Li

Shamit Kapadia

Peter Weinberger

Satyajeet Randhawa

Mandeep S Baines

In one embodiment, a physical device (e.g., packet switching device, computer, server) is booted using custom-created frozen partially-booted virtual machines, avoiding the time required for an end-to-end boot process. In one embodiment while the system is operating under a current version, a partially-booted virtual image of a new operating version for each of multiple processing elements of the device is produced according to static configuration information specific to the device, with each of these partially-booted virtual machines frozen. The device is rebooted to a fully operational device by unfreezing these partially-booted virtual machines, thus removing this portion of a boot process from the real-time booting of the device. The generation of the frozen partially-booted virtual machines is advantageously performed by the device itself based on current static configuration information and the availability of the specific hardware configuration of the device.

Booting a physical device using custom-created frozen partially-booted virtual machines

System and method for generating hardware accelerators and processor offloads. System for hardware acceleration. System and method for implementing an asynchronous offload. Method of automatically creating a hardware accelerator. Computerized method for automatically creating a test harness for a hardware accelerator from a software program. System and method for interconnecting hardware accelerators and processors. System and method for interconnecting a processor and a hardware accelerator. Computer implemented method of generating a hardware circuit logic block design for a hardware accelerator automatically from software. Computer program and computer program product stored on tangible media implementing the methods and procedures of the invention.

Hardware accelerator test harness generation

In one embodiment, a packet switching device creates multiple virtual packet switching devices within the same physical packet switching device using virtual machines and sharing particular physical resources of the packet switching device. One embodiment uses this functionality to change the operating version (e.g., upgrade or downgrade) of the packet switching device by originally operating according to a first operating version, operating according to both a first and second operating version, and then ceasing operating according to the first operating version. Using such a technique, a packet switching device can be upgraded or downgraded while fully operating (e.g., without having to reboot line cards and route processing engines).

Virtual machines in a packet switching device

Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host, the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.

Structured block transfer module, system architecture, and method for transferring

Structured block transfer module, system architecture, and method for transferring content or data. Circuit allowing content in one memory to be shifted, moved, or copied to another memory with no direction from a host., the circuit comprising: a connection manager, at least one copy engine, and a connection between the connection manager and the copy engine. Method for transferring the contents of one of a number of blocks of source memory to one of a number of possible destination memories comprising: selecting source memory; selecting available destination memory; marking the selected destination as no longer available; copying contents of selected source memory into selected destination memory; and marking selected source as available.

In one embodiment, an operating system kernel and/or one or more processes of a high-availability system are modified while the system is operating and providing high-availability service. In accomplishing this, one embodiment uses a second virtual machine to operate a second operating system kernel including a second set of processes in the standby mode, which receive state information from corresponding process(es) in the active mode. Individually, the operating system kernel and processes within the second set of processes may be a same or different version of their counterpart in a first virtual machine and its processes which are being replaced. When the second set of processes have acquired sufficient state information to perform the standby role, the operation of the first virtual machine is typically ceased as the version modified second virtual machine is performing the version modified functionality of the first virtual machine.

Service version modification of a high-availability system

Generating hardware accelerators and processor offloads

Packet ingress/egress block and logic and system and method for receiving, transmitting, and managing packetized data. System including a line port; a computing resource output port; a host interface; a memory, and a block that: receives information on the line port, creates a context including information for managing computation derived from the received information, and sends context out on computing resource output port. Device comprising first circuit component including line port that receives information, second circuit component that generates context information including an information for managing computation derived from the received unit of information; and third circuit component that communicates the generated context out to a computing resource output port. Method comprising receiving information, generating context information including an information for managing computation derived from the received unit of information; and communicating the generated context information out to an external receiver via a computing resource output port.

Packet ingress/egress block and system and method for receiving, transmitting, and managing packetized data

An apparatus, method, and computer-readable program code for dynamically controlling slip is disclosed. The method monitors the time of an actual interrupt, wakes up, interacts with the physical environment, and then notes the completion time and reduces a wait period. The wait period ends in a scheduled interrupt time. By reducing the wait period based on the difference between the actual interrupt time (instead of the scheduled interrupt time) and the completion time, slip is prevented from accumulating and is reduced.

Apparatus, method and computer program for dynamic slip control in real-time scheduling

Method, computer program, system and apparatus for operating system dynamic event management and task scheduling using function calls. Method, computer program product, and system for non-preemptively scheduling tasks in a computer system. Scheduler and scheduling method that schedules tasks that are broken into a number of short actions, without preempting the actions as they are executed and without assigning a priority to tasks. Invention decreases the overhead as compared to existing methods and systems.

Method, computer program and apparatus for operating system dynamic event management and task scheduling using function calls

Method, system, apparatus and computer program product for interrupt scheduling in processing communication. In one embodiment the method includes: a sending computer program and a receiving computer program, coupling at least one registered signal identifier and a corresponding registered signal function with said receiving computer program; sending a communication including a request signal identifier by said sending computer program to said receiving computer program; receiving said communication sent at (B) by said receiving computer program; and performing said corresponding registered signal function without context switching of said receiving computer program if said request signal identifier received is coupled with said registered signal identifier. A system, router, computer program and computer program product are also disclosed.

System, method, and computer program product for interrupt scheduling in processing communication

In summary, one aspect of the present invention is directed to a method for a shared memory queue to support communicating between computer processes, such as an enqueuing process and a dequeuing process. A buffer may be allocated including at least one element having a data field and a reserve field, a head pointer and a tail pointer. The enqueuing process may enqueue a communication into the buffer using mutual exclusive access to the element identified by the head pointer. The dequeuing process may dequeue a communication from the buffer using mutual exclusive access to the element identified by the tail pointer. Mutual exclusive access to said head pointer and tail pointer is not required. A system and computer program for a shared memory queue are also disclosed.

Growing community of inventors

San Jose, CA, United States of America

Akash Renukadas Deshpande