Cadence Design Systems, Inc.

Akash Khandelwal

Rajarshi Mukherjee

Oleg Levitsky

Amit Kumar

Sushobhit Singh

Pawan Kulshreshtha

Manish Garg

Sourav Kumar Sircar

Lalit Bharat

Marc Heyberger

Manish Bhatia

Anurag Saran

Namrata M Sadhankar

Chunlong Pan

Renuka Deshpande

Ruchir Agarwal

Chih-kuo Yu

Disclosed are methods, systems, and articles of manufacture for implementing an electronic design with high-capacity design closure. A reduced netlist may be generated for an analysis view of an electronic design based at least in part upon logic of interest in the analysis view. A closure may be performed based at least in part upon a union netlist, wherein the union netlist is generated from the reduced netlist. The electronic design may then be implemented based at least in part upon a result of the closure task.

Methods, systems, and computer program product for implementing an electronic design with high-capacity design closure

A system and method for generating standard delay format (SDF) files is disclosed. For each timing closed hierarchical instance, timing arcs on internal register to register paths may be marked as zero delay arcs. If the zero delay causes a hold violation, an adjustment may be computed to fix the violation. If the adjustment does not cause a setup violation, the adjustment may be applied to the end point register.

System and method for generating reduced standard delay format files for gate level simulation

A method of timing analysis of an integrated circuit (IC) design with a partition block including an original clock signal with a pair of clock paths having an external common point outside the block boundary is disclosed, including receiving a netlist of the partition block of a hierarchical IC design, analyzing a pair of clock paths having the external common point to determine first and second clock ports at the boundary of the partition block; and for the first and second clock ports, creating launch and capture clocks, making exclusive clock groups of the launch clock and the capture clock for opposing clock ports to avoid the launch and capture clocks for each port affecting other internal data paths within the partition block, and associating common path pessimism removal information with a source latency of the capture clock to adjust timing at an end point of the internal data path.

Common path pessimism removal for hierarchical timing analysis

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Cupertino, CA, United States of America

Akash Khandelwal