Synopsys, Inc.

Akash Jain

Qiang Chen

Sridhar Tirumala

A design optimization method for a target circuit design specified by a machine-readable file, comprises providing a computer-implemented model as a function of a set of characteristics of circuit designs of circuit optimization achievable due to a circuit modification procedure, such as timing constrained gate length modification for leakage power reduction. Using values of said set of characteristics for the target circuit design, the computer-implemented model is applied to the target circuit design to produce an indication of susceptibility of the target circuit design to optimization. The model can be produced using Monte Carlo simulations of a set of virtual designs, and fitting a function of said characteristics to the results.

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Milpitas, CA, United States of America

Akash Jain