Rambus Inc.

Intel Corporation

Kinderlime, Inc.

Akash Bansal

Wayne Frederick Ellis

Brian S Leibowitz

Wayne S Richardson

Lawrence Lai

Kishore Ven Kasamsetty

Frederick Abbott Ware

Yohan Usthavia Frans

Kyung Suk Oh

Hae-Chang Lee

Jade M Kizer

Ian P Shaeffer

Fan Ho

David A Secker

Thomas Hastings Greer

Ely K Tsern

John Welsford Brooks

Simon Li

Todd W Bystrom

Arun Vaidyanath

Anujan Varma

Thomas H Greer, Iii

Donald A Draper

Michael J Sobelman

Jaisimha Bannur

Nalin Pradeep Senthamil

Thomas H Greer Iii

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

High-speed signaling systems and methods with adaptable, continuous-time equalization

A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.

Memory device comprising programmable command-and-address and/or data interfaces

The disclosed embodiments relate to components of a memory system that support timing-drift calibration. In specific embodiments, this memory system contains a memory device (or multiple devices) which includes a clock distribution circuit and an oscillator circuit which can generate a frequency, wherein a change in the frequency is indicative of a timing drift of the clock distribution circuit. The memory device also includes a measurement circuit which is configured to measure the frequency of the oscillator circuit.

Timing-drift calibration

In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

Protocol for memory power-mode control

Display screen with graphical user interface for preschool operations

Growing community of inventors

Santa Clara, CA, United States of America

Akash Bansal