Arm Limited

Akash Bangalore Srinivasa

Yew Keong Chong

Andy Wangkun Chen

Penaka Phani Goberu

Sriram Thyagarajan

Lalit Gupta

Akshay Kumar

Shri Sagar Dwivedi

Vivek Nautiyal

Jitendra Dasani

Vikash

Munish Kumar

Gaurav Rattan Singla

Khushal Gelda

Sujit Kumar Rout

Balaji Ravikumar

Vibin Vincent

Sreebin Sreedhar

Arjunesh Namboothiri Madhavan

Various implementations described herein are related to a device having multi-port circuit architecture with multiple ports. The multi-port circuit architecture may expand a primary clock into multiple dummy clocks so as to separately track, simulate and report clock power consumption for each port of the multiple ports to a central processing unit.

Multi-port circuit architecture

Various implementations described herein are directed to a device having first circuitry with wordline drivers coupled to wordlines. The device may have second circuitry with switch structures that are coupled between a first voltage and ground. The switch structures may be configured to provide a second voltage to a power connection of each wordline driver based on the first voltage.

Wordline driver architecture

Various implementations described herein are related to a device having memory circuitry with an array of bitcells coupled to a power rail. The device may have pulse-bias circuitry with stacks of transistors that are coupled to the power rail. In various instances, the stacks of transistors may be alternately activated so as to thereby provide a pulse-biased power supply to the array of bitcells via the power rail.

Memory architecture with pulsed-bias power

Various implementations described herein are directed to an integrated circuit having memory circuitry with an array of bitcells. The integrated circuit may include read-write circuitry that is coupled to the memory circuitry to perform read operations and write operations for the array of bitcells. The integrated circuit may include write assist circuitry that is coupled to the memory circuitry and the read-write circuitry. The write assist circuitry may receive a control signal from the read-write circuitry. Further, the write assist circuitry may sense write operations based on the control signal and may drive the write operations for the array of bitcells.

Write assist circuitry

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Bengaluru, India

Akash Bangalore Srinivasa