Texas Instruments Corporation

Ajith Subramonia

Parvinder Kumar Rana

Dharin Nayeshbhai Shah

Vipul Kumar Singhal

Girishankar Gurumurthy

Srinivasa Raghavan Sridhara

Atul Ramakant Lele

Raviprakash Suryanarayana Rao

Keshav Bhaktavatson Chintamani

Premkumar Seetharaman

Pavan Vithal Torvi

Malav Shrikant Shah

Sanjeev Kumar Suman

Bharath Kumar Poluri

A system on a chip (SOC) includes a processor and a memory system coupled to the processor. The memory system includes a static random access memory (SRAM) bank and a memory controller. The SRAM bank includes a first switch coupled to a SRAM array power supply and a source of a transistor of an SRAM storage cell in an SRAM array. The SRAM bank also includes a second switch coupled to a NWELL power supply and a bulk of the transistor of the SRAM storage cell. The second switch is configured to close prior to the first switch closing during power up of the SRAM array.

Automatic latch-up prevention in SRAM

Improving routability of an integrated circuit (IC) design without impacting the area is described. A local region of congestion of an IC design is determined according to a design parameter. A cell with a specified level of complexity is identified within the local region of congestion. An alternative cell is algorithmically created with a same logic function as the cell by adding an access point to the alternative cell. The cell is then replaced with the alternative cell within the local region of congestion.

Improving routability of integrated circuit design without impacting the design area

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Bengaluru, India

Ajith Subramonia