International Business Machines Corporation

Ajith Kumar M Chandrasekaran

Sourav Saha

Christopher J Berry

Shyam Ramji

Randall J Darden

Harry S Barowski

Joachim Keinert

Harald Folberth

A system and method place unit-level components in a macro within a unit of an integrated circuit that includes two or more of the units that each include two or more of the macros. The method includes detecting white space in a congestion plot of the macro. The white space represents potential placement areas for the unit-level components. The method also includes performing wire reach analysis between sources and sinks on different sides of the macro to determine an allowable region for the unit-level components, and deriving a buffer and latch placement reservation area in which to place the unit-level components based on the white space and the allowable region.

Placement clustering-based white space reservation

A method and system to perform physical synthesis in a chip design process using hierarchical wire-pin co-optimization are described. The method includes providing boundary conditions to each of a plurality of macros of the chip design from a unit level controller, the boundary conditions including initial pin locations and an indication of which of the pins are movable pins for each of the plurality of macros, performing macro-level physical synthesis at each of the plurality of macros, and providing feedback to the unit level controller based on the macro-level physical synthesis performed at each of the plurality of macros, the feedback including a proposed new location for the movable pins of each of the plurality of blocks. The method also includes performing hierarchical co-optimization at the unit level controller based on the feedback from each of the plurality of macros to determine locations for the movable pins.

Hierarchical wire-pin co-optimization

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Karnataka, India

Ajith Kumar M Chandrasekaran