Western Digital Technologies, Inc.

Ajith Kumar B

Arun Kumar Medapati

Ashwin Narasimha

Sri Rama Namala

Krishanth Skandakumaran

Techniques for controlling power on a PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method for controlling power including providing power to a memory attached via the PCIe interface; monitoring a state of the attached memory; determining whether a new operation to be implemented on the attached memory would cause the power provided to the memory to exceed a preset threshold; and stalling execution of the new operation on the attached memory when it is determined that the new operation would exceed the preset threshold while continuing execution of preexisting operations on the attached memory.

System and method for controlling PCIe direct attached nonvolatile memory storage subsystems

A storage device may include a non-volatile memory; and a controller. The controller may be configured to store a plurality of blocks of data in the memory, determine exclusive-or (XOR) parity data for the plurality of blocks, and store the XOR parity data in the memory; store a second block of data in the memory. The controller may be further configured to generate updated XOR parity data by at least XORing a first block of the plurality of blocks and the second block of data with the XOR parity data to remove the first block from the XOR parity data and to add the second block to the XOR parity data, and store the updated XOR parity data in the memory.

Updating exclusive-or parity data

Techniques for controlling PCIe direct attached non-volatile memory storage system are disclosed. In one particular embodiment, the techniques may be realized as a method including monitoring a temperature of a memory attached via the PCIe interface, determining whether an operation implemented on the attached memory has caused the temperature of the memory to exceed a preset threshold, and controlling an I/O rate of the attached memory based on the determination such that the I/O rate is greater than zero.

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Bengaluru, India

Ajith Kumar B