Texas Instruments Corporation

Other

Ajith E Amerasekera

Thomas A Vrotsos

Julian Zhiliang Chen

Amitava Chatterjee

Srikanth Krishnan

Zhiliang Julian Chen

Xin Yi Zhang

The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit () comprising at least one input element () is protected by a protective circuit (). The protective circuit () is operable to protect the integrated circuit () from damage due to electrostatic discharge and may be coupled to the input element (). The protective circuit () comprises a lateral NPN transistor (T) coupled to the input element () and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (). The protective circuit () also may comprise a lateral PNP transistor (T) coupled to the input element () and to the lateral NPN transistor (T). The lateral PNP transistor (T) is operable to aid in raising a potential of the base of the lateral NPN transistor (T). Alternatively, the protective circuit () also may use a PMOS transistor (P), or a PMOS transistor (P) in combination with the lateral NPN transistor (T), coupled to the input element () and to the lateral NPN transistor (T). The PMOS transistor (P) is operable to aid in raising the potential of the base of the lateral NPN transistor (T).

System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing

One embodiment of the instant invention is a charge-induced damage protection device (100 or 500) for protecting a semiconductor device (200) which is formed on a common substrate with the protection device, the protection device comprising: a region in the substrate; and wherein the region is accessible to electromagnetic energy during processing in which charges may collect on conductive material such that the protective device turns on at a lower voltage due to introduction of the electromagnetic energy to the region so as to protect the semiconductor device from the charge-induced damage. Preferably, the protection device is selected from the group consisting of: a diode, a thyristor, a bidirectional thyristor, a bipolar transistor, and a polymer that becomes more conductive upon being illuminated by electromagnetic energy. The protection device of this embodiment may include a layer situated above the substrate, the layer having an opening (102) above the active region such that the electromagnetic energy passes through the opening to the active region. In another embodiment, the protection device would include a layer situated above the substrate, the electromagnetic energy passing between the substrate and the layer so as to illuminate the active region.

Plasma emission triggered protection device for protecting against

The present invention provides a high efficiency ESD circuit that requires less space through uniform activation of multiple emitter fingers of a transistor structure containing an integral Zener diode. The Zener diode is able to lower the protection circuit trigger threshold from around 18 volts to around 7 volts. This method minimizes series impedance of the signal path, thereby rendering an NPN structure that is particularly well suited for protecting bipolar and CMOS input and output buffers. The ESD circuit of the present invention provides a relatively low shunt capacitance (typically &lt;0.5 pF) and series resistance (typically &lt;0.5 ohm) that are desirable for input and output circuits of present and future contemplated generations of sub-micron bipolar/BiCMOS circuit processes.

ESD protection circuit using zener diode and interdigitated NPN

The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz-&gt;2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the NPN transistor. The turn-on voltage of the Zener is selected so as to be comparable to the emitter-base breakdown voltage of the NPN structure, which is only slightly higher than the power supply voltage to ensure that the ESD protection circuit will not be triggered under normal circuit operation. A forward diode string can optionally be added in series with the Zener to increase circuit trigger voltage, particularly in instances where the power supply voltage exceeds the Zener breakdown voltage. During an ESD event, when pad voltage exceeds Zener breakdown voltage, the Zener breaks down, and current flows through an associated (polysilicon) resistor to trigger the NPN of the Bipolar SCR and thus activate the BSCR to conduct the High ESD current from the associated, protected circuit.

Bipolar SCR triggering for ESD protection of high speed bipolar/BiCMOS

The invention provides a Bipolar structure such as a silicon controlled rectifier (SCR) that exhibits advantageously low triggering and holding voltages for use in high speed (e.g., 900 MHz-&gt;2 GHz) submicron ESD protection circuits for Bipolar/BiCMOS circuits. The Bipolar structure features a low shunt capacitance and a low series resistance on the input and output pins, allowing for the construction of ESD protection circuits having small silicon area and little to no impedance added in the signal path. In a preferred aspect of the invention, the SCR is assembled in the N-well of the Bipolar/BiCMOS device, as opposed to the P-substrate, as is customary in the prior art. A preferred aspect of the invention utilizes a Zener diode in combination with a resistor to control BSCR operation through the PNP transistor. The turn-on voltage of the Zener is selected so as to be comparable to the emitter-base breakdown voltage of the NPN structure, which is only slightly higher than the power supply voltage to ensure that the ESD protection circuit will not be triggered under normal circuit operation. During an ESD event, when pad voltage exceeds Zener breakdown voltage, the Zener breaks down, and current flows through an associated (polysilicon) resistor to trigger the PNP of the Bipolar SCR and thus activate the BSCR to conduct the High ESD current from the associated, protected circuit. BSCR resistance and Zener diode breakdown voltage values are selected which permit scaling of ESD protection circuit holding and trigger voltages for optimum compatibility with the power supply voltage.

Adjustable Bipolar SCR holding voltage for ESD protection circuits in

An npn transistor having a low collector-base breakdown voltage. An emitter region (104, 106) of a first conductivity type is located in a semiconductor substrate (102). A base region (14) of a second conductivity type is located within the emitter region (104,106) and a shallow collector region (18) of the first conductivity type is located within the base region (14). The shallow collector region (18) may be doped with arsenic and/or phosphorus such that the dopant concentration and depth of the shallow collector region (18) provide a low collector-base breakdown voltage.

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Plano, TX, United States of America

Ajith E Amerasekera