Synopsys, Inc.

Ajit Sequeira

Subramanyam Sripada

Yogesh Dilip Save

Abhishek Nandi

Subrahmanya Narasimha Murthy Palla

Shubhashish Rudra

Kirti Kedia

Gowrishankar N J

A first set of timing relationships may be determined in a first circuit design based on a first set of timing constraints specified for the first circuit design. A second set of timing relationships may be determined in a second circuit design based on a second set of timing constraints specified for the second circuit design. The first set of timing relationships may be compared with the second set of timing relationships to obtain a comparison result. Equivalency between the first set of timing constraints and the second set of timing constraints may be determined based on the comparison result.

Performing timing constraint equivalence checking on circuit designs

A method, a system, and a non-transitory computer readable medium are provided. The method includes performing, by one or more computing devices, a lookahead scan of a file of a circuit design to extract information associated with a query in an iterative loop, performing an action to retrieve attribute information from one or more partitions of the circuit design before executing the iterative loop, and querying the iterative loop using the stored attribute information. The action stores the attribute information based on the extracted information.

Runtime and memory efficient attribute query handling for distributed engine

A mode of a circuit design is simplified by eliminating clocks and corresponding timing exceptions and timing constraints from the mode. A system receives a description of a mode of a circuit. The system identifies sets of clock pairs and corresponding timing exceptions associated with timing nodes of the mode, each clock pair comprising a launch clock and a capture clock. The system compares time intervals between an edge of the launch clock and a corresponding edge of the capture clock for the clock pairs subject to timing exceptions associated with the timing path. The system identifies certain clock pairs as critical based on a comparison of the time interval associated with each clock pair. The system simplifies the mode by eliminating non-critical clocks and corresponding timing exceptions. The modified mode is used for performing timing analysis.

Simplifying modes of an electronic circuit by reducing constraints

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Bengaluru, India

Ajit Sequeira