Innovium, Inc.

Marvell Asia Pte., Ltd.

Ajit Kumar Jain

Puneet Agarwal

William Brad Matthews

Mohammad Kamel Issa

Ashwin Alapati

Bruce Hui Kwan

Avinash Gyanendra Mani

Srinivas Gangam

William Fan

Anurag Kumar Jain

A scheduler in a network device serves ports with data units from a plurality of queues. The scheduler implements a scheduling algorithm that is normally constrained to releasing data to a port no more frequently than at a default maximum service rate. However, when data units smaller than a certain size are at the heads of one or more data unit queues assigned to a port, the scheduler may temporarily increase the maximum service rate of that port. The increased service rate permits fuller realization of a port's maximum bandwidth when handling smaller data units. In some embodiments, increasing the service rate involves dequeuing more than one small data unit at a time, with the extra data units temporarily stored in a port FIFO. The scheduler adds a pseudo-port to its scheduling sequence to schedule release of data from the port FIFO, with otherwise minimal impact on the scheduling logic.

Efficient scheduling using adaptive packing mechanism for network apparatuses

Approaches, techniques, and mechanisms are disclosed for efficiently buffering data units within a network device. A traffic manager or other network device component receives Transport Data Units ('TDUs'), which are sub-portions of Protocol Data Units (“PDUs”). Rather than buffer an entire TDU together, the component divides the TDU into multiple Storage Data Units (“SDUs”) that can fit in SDU buffer entries within physical memory banks. A TDU-to-SDU Mapping (“TSM”) memory stores TSM lists that indicate which SDU entries store SDUs for a given TDU. Physical memory banks in which the SDUs are stored may be grouped together into logical SDU banks that are accessed together as if a single bank. The TSM memory may include a number of distinct TSM banks, with each logical SDU bank having a corresponding TSM bank. Techniques for maintaining inter-packet and intra-packet linking data compatible with such buffers are also disclosed.

Efficient buffer utilization for network data units

Link data is stored in a distributed link descriptor memory ('DLDM') including memory instances storing protocol data unit (“PDU”) link descriptors (“PLDs”) or cell link descriptors (“CLDs”). Responsive to receiving a request for buffering a current transfer data unit (“TDU”) in a current PDU, a current PLD is accessed in a first memory instance in the DLDM. It is determined whether any data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD. If no data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD, a current CLD is accessed in a second memory instance in the plurality of memory instances of the same DLDM. Current address information in connection with the current TDU is stored in an address data field within the current CLD.

Distributed link descriptor memory

A first component of a network device determines that the first component is to provide packet data to a second component of the network device for processing by the second component. In connection with determining that the first component is to provide packet data to the second component of the network device, the first component prompts the second component to activate a clock network of the second component. In connection with prompting the second component to activate the clock network, the first component sends the packet data to the second component to be processed by the second component. The first component determines when the second component has completed processing of the packet data, and prompts the second component to deactivate the clock network in response to determining that the second component has completed processing of the packet data.

Power saving in a network device

A network device implements a foldable ingress buffer for buffering data units as they are being received. The buffer is organized into a grid of memory banks, having different columns and rows. A Transport Data Unit ('TDU') is stored interleaved across entries in multiple banks. As each portion of a TDU is received, the portion is written to a different bank of the buffer. In each column of the buffer, a full-sized TDU has portions in a number of rows equal to the number of folds in the buffer. The sum of the bank widths for each row thus needs be no larger than half the maximum TDU size, which further means that the number of columns in the grid of banks may be reduced by at least half compared to non-folded approaches, with little increase in the number of rows, if any, depending on blocking and reading requirements.

Foldable ingress buffer for network apparatuses

When a measure of buffer space queued for garbage collection in a network device grows beyond a certain threshold, one or more actions are taken to decreasing an enqueue rate of certain classes of traffic, such as of multicast traffic, whose reception may have caused and/or be likely to exacerbate garbage-collection-related performance issues. When the amount of buffer space queued for garbage collection shrinks to an acceptable level, these one or more actions may be reversed. In an embodiment, to more optimally handle multi-destination traffic, queue admission control logic for high-priority multi-destination data units, such as mirrored traffic, may be performed for each destination of the data units prior to linking the data units to a replication queue. If a high-priority multi-destination data unit is admitted to any queue, the high-priority multi-destination data unit can no longer be dropped, and is linked to a replication queue for replication.

Multi-destination traffic handling optimizations in a network device

A network device organizes packets into various queues, in which the packets await processing. Queue management logic tracks how long certain packet(s), such as a designated marker packet, remain in a queue. Based thereon, the logic produces a measure of delay for the queue, referred to herein as the 'queue delay.' Based on a comparison of the current queue delay to one or more thresholds, various associated delay-based actions may be performed, such as tagging and/or dropping packets departing from the queue, or preventing addition enqueues to the queue. In an embodiment, a queue may be expired based on the queue delay, and all packets dropped. In other embodiments, when a packet is dropped prior to enqueue into an assigned queue, copies of some or all of the packets already within the queue at the time the packet was dropped may be forwarded to a visibility component for analysis.

Delay-based tagging in a network switch

Link data is stored in a distributed link descriptor memory ('DLDM') including memory instances storing protocol data unit ('PDU') link descriptors ('PLDs') or cell link descriptors (&#x201c;CLDs&#x201d;). Responsive to receiving a request for buffering a current transfer data unit (&#x201c;TDU&#x201d;) in a current PDU, a current PLD is accessed in a first memory instance in the DLDM. It is determined whether any data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD. If no data field designated to store address information in connection with a TDU is currently unoccupied within the current PLD, a current CLD is accessed in a second memory instance in the plurality of memory instances of the same DLDM. Current address information in connection with the current TDU is stored in an address data field within the current CLD.

A network traffic manager receives, from an ingress port in a group of ingress ports, a cell of a packet destined for an egress port. Upon determining that a number of cells of the packet stored in a buffer queue meets a threshold value, the manager checks whether the group of ingress ports has been assigned a token for the queue. Upon determining that the group of ingress ports has been assigned the token, the manager determines that other cells of the packet are stored in the buffer, and accordingly stores the received cell in the buffer, and stores linking information for the received cell in a receive context for the packet. When all cells of the packet have been received, the manager copies linking information for the packet cells to the buffer queue or a copy generator queue, and releases the token from the group of ingress ports.

Processing packets in an electronic device

Network chip utility is improved using multi-core architectures with auxiliary wiring between cores to permit cores to utilize components from otherwise inactive cores. The architectures permit, among other advantages, the re-purposing of functional components that reside in defective or otherwise non-functional cores. For instance, a four-core network chip with certain defects in three or even four cores could still, through operation of the techniques described herein, be utilized in a two or even three-core capacity. In an embodiment, the auxiliary wiring may be used to redirect data from a Serializer/Deserializer ('SerDes') block of a first core to packet-switching logic on a second core, and vice-versa. In an embodiment, the auxiliary wiring may be utilized to circumvent defective components in the packet-switching logic itself. In an embodiment, a core may utilize buffer memories, forwarding tables, or other resources from other cores instead of or in addition to its own.

Growing community of inventors

Cupertino, CA, United States of America

Ajit Kumar Jain