Xilinx, Inc.

Ajit K Agarwal

Ralph D Wittig

Philip Bryn James-Roxby

Vinod Kumar Kathail

Shail Aditya Gupta

Mukund Sivaraman

Samuel R Bayliss

Akella Sastry

Rishi Surendran

Kumud Bhandari

A computer-based technique for processing an application includes determining that a loop of the application includes a reference to a data item of a vector data type. A trip count of the loop is determined to have an unknown trip count. The loop is split into a first loop and a second loop based on a splitting factor. The second loop is unrolled.

Splitting vector processing loops with an unknown trip count

Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges. A compiler converts the source code into a bit stream and/or object code which configures a heterogeneous processing environment of a SoC to execute the graph. Before implementing the dataflow graph on the SoC, the programmer may wish to simulate the dataflow graph. In one embodiment, each kernel in the dataflow graph is assigned a respective thread. Additionally, the simulator can include a runtime library for simulating the different types of communication links between the kernels. Even those these communication links are different protocols or have different semantics, using the simulation components in the library makes the different types of communication links composable so they can inter-operate in the same simulation environment.

Multi-threaded shared memory functional simulation of dataflow graph

An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array includes determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.

Compilation flow for a heterogeneous multi-core architecture

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Hyderabad Telangana, India

Ajit K Agarwal