Georgia Tech Research Corporation

Suniva, Inc.

Westinghouse Electric Corporation

Ajeet Rohatgi

Vinodh Chandrasekaran

Vijay Yelundur

Preston Davis

Ben Damiani

Zhizhang Chen

Daniel L Meier

Robert K Feeney

David R Hertling

Parag Doshi

Vichai Meemongkolkiat

Stephen J Fonash

William Alan Doolittle

Michael Ropp

Prosenjit Rai-Choudhury

Joseph R Gigante

Miroslav M Begovic

John Keith Tate

Thomas W Krygowski

Ranbir Singh

Jose Mejia

Brian Rounsaville

Kenta Nakayashiki

Dong Seop Kim

Solar cells and methods for their manufacture are disclosed. An example method may include providing a substrate comprising a base layer and introducing n-type dopant to the front surface of the base layer by ion implantation. The substrate may be annealed by heating the substrate to a temperature to anneal the implant damage and activate the introduced dopant, thereby forming an n-type doped layer into the front surface of the base layer. Oxygen may be introduced during the annealing step to form a passivating oxide layer on the n-type doped layer. Back contacts may be screen-printed on the back surface of the base layer, and a p-type doped layer may be formed at the interface of the back surface of the base layer and the back contacts during firing of the back contacts. The back contacts may provide an electrical connection to the p-type doped layer.

Ion implanted solar cells with in situ surface passivation

A thin silicon solar cell is described. An example solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer. A final layer of transparent conductive oxide is formed on both sides. Metal contacts are applied to the transparent conductive oxide.

Method for making solar cell having crystalline silicon P&#x2014;N homojunction and amorphous silicon heterojunctions for surface passivation

Solar cells and methods for their manufacture are disclosed. An example solar cell may comprise a substrate comprising a p-type base layer and an n-type selective emitter layer formed over the p-type base layer. The n-type selective emitter layer may comprise one or more first doped regions comprising implanted dopant and one or more second doped regions comprising diffused dopant. The one or more first doped regions may be more heavily doped than the one or more second doped regions. A p-n junction may be formed at the interface of the base layer and the selective emitter layer, such that the p-n junction and the selective emitter layer are both formed during a single anneal cycle.

Selective emitter solar cells formed by a hybrid diffusion and ion implantation process

Solar cells and methods for their manufacture are disclosed. An example method may include providing a p-type doped silicon substrate and introducing n-type dopant to a first and second region of the front surface of the substrate by ion implantation so that the second region is more heavily doped than the first region. The substrate may be subjected to a single high-temperature anneal cycle to activate the dopant, drive the dopant into the substrate, produce a p-n junction, and form a selective emitter. Oxygen may be introduced during the single anneal cycle to form in situ front and back passivating oxide layers. Fire-through of front and back contacts as well as metallization with contact connections may be performed in a single co-firing operation. Associated solar cells are also provided.

Ion implanted selective emitter solar cells with in situ surface passivation

A thin silicon solar cell is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness of approximately 50 micrometers to 500 micrometers. The solar cell comprises a first region having a p-n homojunction, a second region that creates heterojunction surface passivation, and a third region that creates heterojunction surface passivation. Amorphous silicon layers are deposited on both sides of the silicon wafer at temperatures below approximately 400 degrees Celsius to reduce the loss of passivation properties of the amorphous silicon. A final layer of transparent conductive oxide is formed on both sides at approximately 165 degrees Celsius. Metal contacts are applied to the transparent conductive oxide. The low temperatures and very thin material layers used to fabricate the outer layers of used to fabricate the outer layers of the solar cell protect the thin wafer from excessive stress that may lead to deforming the wafer.

Method for making solar cell having crystalline silicon P-N homojunction and amorphous silicon heterojunctions for surface passivation

Solar cells and methods for their manufacture are disclosed. An example method may include providing a silicon substrate and introducing dopant to one or more selective regions of the front surface of the substrate by ion implantation. The substrate may be subjected to a single high-temperature anneal cycle. Additional dopant atoms may be introduced for diffusion into the front surface of the substrate during the single anneal cycle. A selective emitter may be formed on the front surface of the substrate such that the one or more selective regions of the selective emitter layer are more heavily doped than the remainder of the selective emitter layer. Associated solar cells are also provided.

A thin silicon solar cell having a back dielectric passivation and rear contact with local back surface field is described. Specifically, the solar cell may be fabricated from a crystalline silicon wafer having a thickness from 50 to 500 micrometers. A barrier layer and a dielectric layer are applied at least to the back surface of the silicon wafer to protect the silicon wafer from deformation when the rear contact is formed. At least one opening is made to the dielectric layer. An aluminum contact that provides a back surface field is formed in the opening and on the dielectric layer. The aluminum contact may be applied by screen printing an aluminum paste having from one to 12 atomic percent silicon and then applying a heat treatment at 750 degrees Celsius.

Method for formation of high quality back contact with screen-printed local back surface field

Disclosed are various embodiments that include a process, an arrangement, and an apparatus for boron diffusion in a wafer. In one representative embodiment, a process is provided in which a boric oxide solution is applied to a surface of the wafer. Thereafter, the wafer is subjected to a fast heat ramp-up associated with a first heating cycle that results in a release of an amount of boron for diffusion into the wafer.

Boron diffusion in silicon devices

Method for cleaning a solar cell surface opening made with a solar etch paste

A preferred embodiment of the electrical power system of the present invention includes a power conditioning unit which is configured to receive the DC electrical output signal to deliver an AC output signal to a grid-connected load. Preferably, the power conditioning unit includes a controller which is configured to monitor the AC output signal so that the power conditioning unit may cease delivering the AC output signal when a characteristic of the AC output signal satisfies an established criterion.

Systems and methods for preventing islanding of grid-connected electrical power systems

Disclosed is an arrangement, dopant source and method used in the fabrication of photocells that minimize handling of cell wafers and involve a single furnace step. First, dopant sources are created by depositing selected dopants onto both surfaces of source wafers. The concentration of dopant that is placed on the surface is relatively low so that the sources are starved sources. These sources are stacked with photocell wafers in alternating orientation in a furnace. Next, the temperature is raised and thermal diffusion takes place whereby the dopant leaves the source wafers and becomes diffused in a cell wafer creating the junctions necessary for photocells to operate. The concentration of dopant diffused into a single side of the cell wafer is proportional to the concentration placed on the respective dopant source facing the side of the cell wafer. Then, in the same thermal cycle, a layer of oxide is created by introducing oxygen into the furnace environment after sufficient diffusion has taken place. Finally, the cell wafers receive an anti-reflective coating and electrical contacts for the purpose of gathering electrical charge.

Arrangement, dopant source, and method for making solar cells

Processes which utilize rapid thermal processing (RTP) are provided for inexpensively producing high efficiency silicon solar cells. The RTP processes preserve minority carrier bulk lifetime .tau. and permit selective adjustment of the depth of the diffused regions, including emitter and back surface field (bsf), within the silicon substrate. In a first RTP process, an RTP step is utilized to simultaneously diffuse phosphorus and aluminum into the front and back surfaces, respectively, of a silicon substrate. Moreover, an in situ controlled cooling procedure preserves the carrier bulk lifetime .tau. and permits selective adjustment of the depth of the diffused regions. In a second RTP process, both simultaneous diffusion of the phosphorus and aluminum as well as annealing of the front and back contacts are accomplished during the RTP step. In a third RTP process, the RTP step accomplishes simultaneous diffusion of the phosphorus and aluminum, annealing of the contacts, and annealing of a double-layer antireflection/passivation coating SiN/SiO.sub.x. In a fourth RTP process, the process of applying front and back contacts is broken up into two separate respective steps, which enhances the efficiency of the cells, at a slight time expense. In a fifth RTP process, a second RTP step is utilized to fire and adhere the screen printed or evaporated contacts to the structure.

Processes for producing low cost, high efficiency silicon solar cells

A computer-based deep level transient spectroscopy (DLTS) system (10) efficiently digitizes and analyzes capacitance and conductance transients acquired from a test material (13) by conventional DLTS methods as well as by several transient methods, including a covariance method of linear predictive modeling. A unique pseudo-logarithmic data storage scheme allows each transient to be tested at more than eleven different rates, permitting three to five decades of time constants .tau. to be observed during each thermal scan, thereby allowing high resolution of closely spaced defect energy levels. The system (10) comprises a sensor (12) for detecting capacitance and/or conductance transients, a digitizing mechanism (14) for digitizing the capacitance and/or conductance transients, preamplifiers (16a, 16b) for filtering, amplifying, and for forwarding the transients to the digitizing mechanism (14), a pulse generator (18) for supplying a filling pulse to the test material (13) in a cryostat (24), a trigger conditioner for coordinating the timing between the digitizing mechanism (14) and the pulse generator (18), and a temperature controller (26) for changing the temperature of the cryostat (24).

Deep level transient spectroscopy (DLTS) system and method

Processes which utilize rapid thermal processing (RTP) are provided for inexpensively producing high efficiency silicon solar cells. The RTP processes preserve minority carrier bulk lifetime .tau. and permit selective adjustment of the depth of the diffused regions, including emitter and back surface field (bsf), within the silicon substrate. Silicon solar cell efficiencies of 16.9% have been achieved. In a first RTP process, an RTP step is utilized to simultaneously diffuse phosphorus and aluminum into the front and back surfaces, respectively, of a silicon substrate. Moreover, an in situ controlled cooling procedure preserves the carrier bulk lifetime .tau. and permits selective adjustment of the depth of the diffused regions. In a second RTP process, both simultaneous diffusion of the phosphorus and aluminum as well as annealing of the front and back contacts are accomplished during the RTP step. In a third RTP process, the RTP step accomplishes simultaneous diffusion of the phosphorus and aluminum, annealing of the contacts, and annealing of a double-layer antireflection/passivation coating SiN/SiO.sub.x.

An electrical conductivity tester accurately measures the time-varying electrical conductivity .sigma.(t) and steady-state electrical conductivity .sigma..sub.ss of a test material. In a first embodiment, the transmission phase of a probe circuit is monitored to determine the conductivity of a test material. In the first embodiment, an oscillator circuit generates a reference oscillator signal. A probe circuit receives the reference oscillator signal, magnetically couples to the test material, and modifies the reference oscillator signal via electromagnetic induction to derive a modified transmission phase signal. Finally, a phase detector circuit derives a transmission phase signal by combining the reference oscillator signal and the modified transmission phase signal, the transmission phase signal being directly convertible to the conductivity. In a second embodiment, an amplifier is connected to the probe circuit to form an oscillator circuit. The oscillator circuit generates an oscillator signal in response to the magnetic coupling of the probe circuit with the test material. A frequency discriminator generates a frequency signal from the oscillator signal, the frequency signal being convertible to the conductivity.

Growing community of inventors

Marietta, GA, United States of America

Ajeet Rohatgi