Cavium, Inc.

Brocade Communications Systems, Inc.

Pensando Systems Inc.

Ajeer Salil Pudiyapura

Ravindran Suresh

Kishore Badari Atreya

Wing-Keung Adam Yeung

Mehul Dholakia

Krishna Doddapaneni

Sarat Kamisetty

Ganesan Velrajan

Sarat Babu Kamisetty

Described are programmable input output (IO) devices comprising: an match processing unit (MPU) and a memory unit. The MPU comprising at least one arithmetic logic unit (ALU). The memory unit having instructions stored thereon which, when executed by the respective programmable IO device, cause the programmable IO device to perform operations. These operations comprise: receiving, from an inbound interface, a packet comprising packet data for at least one range-based element; determining, via the MPU, a lookup result by performing a modified binary search on an interval binary search tree with the packet data to determine a longest prefix match (LPM), wherein the interval binary search tree maps the at least one range-based element to an associated data element; and classifying the packet based on the lookup result.

Systems for providing an LPM implementation for a programmable data plane through a distributed algorithm

Described are programmable IO devices configured to perform operations. These operations comprise: determining a set of range-based elements for a network; sorting the set of range-based elements according to a global order among the range-based elements; generating an interval table from the sorted range-based elements; generating an interval binary search tree from the interval table; propagating data stored in subtrees of interior stages of the interval binary search tree to subtrees of a last stage of the interval binary search tree such that the interior stages do not comprise data; converting the interval binary search tree to a Pensando Tree; compressing multiple levels of the Pensando Tree into cache-lines; and assembling the cache-lines in the memory unit such that each stage can compute an address of a next-cache line to be fetched by a next stage.

Systems for building data structures with highly scalable algorithms for a distributed LPM implementation

A processing network including a plurality of lookup and decision engines (LDEs) each having one or more configuration registers and a plurality of on-chip routers forming a matrix for routing the data between the LDEs, wherein each of the on-chip routers is communicatively coupled with one or more of the LDEs. The processing network further including an LDE compiler stored on a memory and communicatively coupled with each of the LDEs, wherein the LDE compiler is configured to generate values based on input source code that when programmed into the configuration registers of the LDEs cause the LDEs to implement the functionality defined by the input source code.

Compiler architecture for programmable application specific integrated circuit based network devices

Algorithm to achieve optimal layout of instruction tables for programmable network devices

Algorithm to derive logic expression to select execution blocks for programmable network devices

Code generator for programmable network devices

Code processor to build orthogonal execution blocks for programmable network devices

A parser engine programming tool configured to receive an input file representing a directly connected cyclical graph or tree of decision points for parsing a range of incoming packet headers, automatically generate all possible paths within the graph and thereby the associated possible headers, and convert the determined paths/headers into a proper format for programming memory of a parser engine to parse the determined headers (represented by the paths).

Parser engine programming tool for programmable network devices

Algorithm to achieve optimal layout of decision logic elements for programmable network devices

Techniques that enable a network device such as a router to provide multicast routing services without interruption, even in the event of a switchover. An incremental updates technique is used to synchronize multicast information maintained by a first processor and multicast information maintained by a second processor. The first processor may be a management processor operating in active mode in a network device and the second processor may be a management processor operating in standby mode in the network device. The second processor may also be a processor on a linecard of the network device.

Synchronization of multicast information using incremental updates

Techniques for organizing and grouping memory contents related to multicast routing so as to enable more efficient multicast operations. For PIM multicast routing, techniques are provided for organizing and grouping multicast routing information into data structures according to a plurality of dimensions such that multicast routing cache entries are accessible when performing a multicast routing operation by traversing the one or more data structures according to at least two of the dimensions.

Multicast route cache system

In embodiments of the present invention, multicast traffic is simultaneously routed via all switches participating in the trunk (can be referred to as partner switches). A respective partner switch synchronizes the local multicast state information with all other partner switches. For a respective multicast group, a plurality of partner switches can be the part of the corresponding multicast distribution tree and obtain multicast traffic from uplink sources. For the multicast group, only one partner switch is elected as the primary forwarder which forwards the multicast traffic via the trunk. Another partner switch can become the primary forwarder for the multicast traffic of another multicast group and provide load sharing of multicast traffic between partner switches. Furthermore, because the partner switches have the multicast traffic and state readily available, in the event of a switch or link failure to the primary forwarder, another partner switch can readily become the primary forwarder.

IP multicast over multi-chassis trunk

In a network device comprising redundant management processors and one or more linecard processors situated on one or more linecards, a linecard processor maintains multicast information that is synchronized with multicast information, or a portion thereof, maintained by an active management processor. When a switchover is performed due to which a previous standby management processor becomes the new active management processor, the switchover is performed without interrupting any multicast routing services provided by the network device. For example, a switchover may be performed in order to upgrade a linecard processor to a new software version.

Synchronizing multicast information for linecards

Techniques that enable a network device such as a router to provide multicast routing services without interruption. Techniques are provided for using bicasting to synchronize multicast information maintained by a first processor and multicast information maintained by a second processor. A multicast protocol related event of packet is sent to both a first processor operating in active mode and a second processor operating in standby mode. Each processor then updates its multicast information based upon the bicasted event or packet.

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Sunnyvale, CA, United States of America

Ajeer Salil Pudiyapura