Intel Corporation

Ajaya V Durg

Oleg B Rashkovskiy

Arvind Mandhani

Ashish V Choubal

Kalyan Muthukumar

Arvind Raman

Sundar Ramani

Samudyatha Chakki

Arojit Roychowdhury

Bran Ferren

Lakshman Krishnamurthy

William W Macy, Jr

Prashant Gandhi

Rahul Pal

Ramanathan Sethuraman

Sayantan Sur

Qingfeng Li

Rajesh Poornachandran

Rajesh M Sankaran

Andrew J Herdrich

David M Puffer

Yen-Cheng Liu

Aravindh V Anantaraman

Todd M Rimmer

Bahaa Fahim

Rajeev D Muralidhar

Bruce L Fleming

Pratik M Marolia

Srinivas Sridharan

Mohammad R Haghighat

Kenneth Foust

Mark Debbage

Vasudev Bibikar

Bruce G Warren

Rajasekaran Andiappan

Tejpal Singh

Vishram Sarurkar

Philip Abraham

Quang T Le

Anil K Sabbavarapu

Rakesh Avichal Ughreja

William Macy

Mikhail E Smorkalov

Arpit Shah

James A Bish

Sudarshan Srinivasan

Nayan Amrutlal Suthar

Moorthy Rajesh

Shilpa Huddar

Sunil Shanbhag

Nabil F Kerkiz

Ryan R Pinto

Ranjani Sridharan

Sanilkumar Mm

Sundar Iyer

Methods and apparatus for an accelerator controller hub (ACH). The ACH may be a stand-alone component or integrated on-die or on package in an accelerator such as a GPU. The ACH may include a host device link (HDL) interface, one or more Peripheral Component Interconnect Express (PCIe) interfaces, one or more high performance accelerator link (HPAL) interfaces, and a router, operatively coupled to each of the HDL interface, the one or more PCIe interfaces, and the one or more HPAL interfaces. The HDL interface is configured to be coupled to a host CPU via an HDL link and the one or more HPAL interfaces are configured to be coupled to one or more HPALs that are used to access high performance accelerator fabrics (HPAFs) such as NVlink fabrics and CCIX (Cache Coherent Interconnect for Accelerators) fabrics. Platforms including ACHs or accelerators with integrated ACHs support RDMA transfers using RDMA semantics to enable transfers between accelerator memory on initiators and targets without CPU involvement.

Accelerator controller hub

Examples described herein relate to a first graphics processing unit (GPU) with at least one integrated communications system, wherein the at least one integrated communications system is to apply a reliability protocol to communicate with a second at least one integrated communications system associated with a second GPU to copy data from a first memory region to a second memory region and wherein the first memory region is associated with the first GPU and the second memory region is associated with the second GPU.

Direct memory writes by network interface of a graphics processing unit

A processor, including a core; and a cache-coherent memory fabric coupled to the core and having a primary cache agent (PCA) configured to provide a primary access path; and a secondary cache agent (SCA) configured to provide a secondary access path that is redundant to the primary access path, wherein the PCA has a coherency controller configured to maintain data in the secondary access path coherent with data in the main access path.

Redundant cache-coherent memory fabric

Systems, apparatuses and methods may provide for technology that detects a runtime call to a communication library, wherein the runtime call identifies a memory buffer, determines that a class of service (CLOS) attribute is associated with the memory buffer, and issues a driver instruction to modify the CLOS attribute in response to the runtime call.

Initialization and management of class of service attributes in runtime to optimize deep learning training in distributed environments

In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Selecting a low power state based on cache flush latency determination

Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.

Enabling system low power state when compute elements are active

In one example a sensor module comprises at least one sensor and a controller communicatively coupled to the at least one sensor by a communication bus, the controller comprising logic, at least partially including hardware logic, configured to generate a signal to configure the at least one sensor in a notify power state mode and place the signal on a communication bus coupled to the at least one sensor. Other examples may be described.

Sensor bus interface for electronic devices

The present disclosure describes techniques related to media caching. A media hub device may include a media hub device configured to execute an operation on a current frame of media having a frame period. The media hub device may include a cache configured to provide, to a media accelerator of the media hub device, data associated with the frame period of the current frame.

Media hub device and cache

An electronic apparatus may be provided that includes a clock device to provide a clock signal, and a clock gate to receive the clock signal, the clock gate to be selectively provided in an enabled state or a disabled state. The electronic apparatus may also include a controller to determine a frequency transition and to control the clock gate to be in the enabled state or the disabled state based on the determined frequency transition.

Dynamic clock gating frequency scaling

Technologies for low-power display refresh standby include a computing device with a display such as an LCD panel. The computing device may include a system-on-a-chip (SoC) with a processor, I/O subsystem, display controller, and memory. When the computing device determines that a display image is static, the computing device enters a low-power display refresh standby mode, powering down unneeded components of the SoC such as processor cores, peripheral devices, and memory other than a dedicated display buffer. The display controller may access the dedicated display buffer via the I/O subsystem and output the image to the display. The computing device may power down the I/O subsystem and the dedicated display buffer when a display controller FIFO is full of image data, and periodically power on the I/O subsystem and display buffer to fill the display controller FIFO. Other embodiments are described and claimed.

Technologies for low-power standby display refresh

Power conservation for mobile device displays. An embodiment of a method includes generating display images for a display screen of a mobile device, and transitioning the mobile device to a reduced power consumption state. The reduced power consumption state includes reducing one or more illumination factors for the display screen; and reducing one or more animation factors for the display screen.

Power conservation for mobile device displays

A method for reducing row noise from a complementary metal oxide semiconductor (CMOS) image sensor is disclosed. The method includes determining a set of row sums for a set of pixel rows in the image sensor and a set of corresponding contributing pixel counts. Then, determining a set of row offset corrections. Finally, adjusting the set of pixel rows by the set of row offset corrections.

Method for reducing row noise from images

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Sunnyvale, CA, United States of America

Ajaya V Durg