Cadence Design Systems, Inc.

Ajay Tomar

Naresh Kumar

Rakesh Agarwal

Prashant Sethia

Umesh Gupta

Manish Bansal

Sourabh Kumar Verma

Kaustav Guha

The present disclosure relates to a system and method for electronic design automation. Embodiments may include receiving, using at least one processor, an electronic design and determining one or more graph based analysis ('GBA') violating nodes associated with the electronic design. Embodiments may include identifying a non-covered violating node from the GBA violating nodes and determining a worst timing path through the non-covered violating node. Embodiments may further include invoking a path-based analysis ('PBA') on the worst timing path and determining if the worst timing path satisfies the PBA analysis.

Comprehensive path based analysis process

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Delhi, India

Ajay Tomar